VHDL tutorial - A practical example - part 3 - VHDL testbench

Gene Breniman June 25, 20115 comments

In part 1 (http://www.embeddedrelated.com/showarticle/85.php) of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part.  In part 2 (http://www.embeddedrelated.com/showarticle/87.php), we described the VHDL logic of the CPLD for this design.  In part 3, we will show the entire VHDL design and the associated tests used to prove that we have, in fact, designed what we started out to...


VHDL tutorial - A practical example - part 2 - VHDL coding

Gene Breniman May 27, 2011

In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part.  In part 2, we will describe the VHDL logic of the CPLD for this design.

With any design, the first step to gather the requirements for the job at hand.  From part 1 of this article, I have copied two sections that address some of the requirements for the CPLD design.

The data acquisition engine has the following basic functions:


VHDL tutorial - A practical example - part 1 - Hardware

Gene Breniman May 18, 20111 comment

In previous posts I described some simple VHDL examples.  This time let's try something a little more complex. This is part one of a multiple part article.  This is intended to be a detailed description of one of several initial designs that I developed for a client.  This design never made it into a product, but a similar design was used and is currently being produced.  As a considerable amount of work was put into this effort, I decided to share this design through this forum as opposed to burying it completely. This design was intended to be a...


VHDL tutorial - Creating a hierarchical design

Gene Breniman May 22, 20086 comments

In earlier blog entries I introduced some of the basic VHDL concepts. First, developing a function ('VHDL tutorial') and later verifying and refining it ('VHDL tutorial - part 2 - Testbench' and 'VHDL tutorial - combining clocked and sequential logic'). In this entry I will describe how to build a VHDL design made up of a collection of...


VHDL tutorial - combining clocked and sequential logic

Gene Breniman March 3, 2008

In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this example, I showed how to generate a clock signal (ADCClk), that was to be programmable over a series of fixed rates (20MHz, 10MHz, 4MHz, 2MHz, 1MHz and 400KHz), given a master clock rate of 40MHz. A reader of that article had written to ask...


Designing Embedded Systems with FPGA-2

Pragnesh Patel November 13, 200711 comments

In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and run time checking. If we use VHDL to write and...


VHDL tutorial - part 2 - Testbench

Gene Breniman October 30, 20073 comments

In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE environment makes it pretty easy to start the testing process. To start the process, select "New Source" from the menu items under "Project". This launches the "New Source Wizard". From within the Wizard select "VHDL Test Bench" and enter the name of the new module (click 'Next' to continue). The "New Source Wizard" then...


Designing Embedded System with FPGA - 1

Pragnesh Patel October 28, 200713 comments

With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.

 

I will start with basic system with FPGA. Xilinx has embedded system...


My first entry to embeddedrelated.com

Pragnesh Patel October 23, 20073 comments

Hello everybody, it’s nice to have an opportunity to write on embedded system and share experiments with readers.

I recently started embedded systems in FPGA having luxury of reconfigurable logics and will like to share some of my thoughts in first post.

I worked with Xilinx SPARTAN 3E and with their embedded system tools known as EDK 9.1 (Embedded Development Kit) software tool, its fun to play with FPGA with no knowledge of VHDL programming. In order to create hardware logic block to perform certain processor independent functions, VHDL programming is...


VHDL tutorial

Gene Breniman October 4, 20077 comments

When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's standards (simple PALs verses FPGA), they were an extremely cost effective tool addressing the need for specialized logic blocks.

I have continued to incorporate these powerful blocks into many of my latest designs. My current favorite part line is the Xilinx CoolRunner series (XC2Cxxx). In this article I will present a cut-down sample of one of my active design projects...