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Discussion Groups | 68HC12 | Bootloader and Vector table.
Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).
Bootloader and Vector table. - bbalend - Apr 18 13:07:00 2005
Looks like my application require two vector table. one for application
and other one is for bootloader. There won't any sci interface
communication, except it will be present for debugging purpose. All
flash erase/programming are performed via the I2C bus.
So, my questions are:
1) Will there be any design issues that I have to watchout for?
2) How do switch/handle two vector table?
3) Which memory space is ideal for the two vector tables?
Note: Bootloader will only be program via the BDM.
Thanks
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
RE: Bootloader and Vector table. - David Wild - Apr 18 14:55:00 2005
In one case that I worked with the interrupt table normally started at FFD0.
I switched the compiler offset to place the application's vector tabel at
F7D0 and then placed the bootloader (with it's reset vector) at F800-FFFF.
There are a variety of ways that you can handle both interrupt vectors,
especially using program counter relative addressing. One way is to simply
point the bootloader's interrupt table vectors to a section of the
bootloader which will load X with an address that is some offset from the
current address, (which would be the application's corresponding interrupt
vector. Then once that address is loaded into X follow the command with a
JMP 0,X. this will set the PC to the address specified in the application's
vector table. The downside is that it adds about 4 or 5 clock cyles to the
interrupt latency, which often is not a big deal.
-Dave
_____
From: 68HC12@68HC... [mailto:68HC12@68HC...] On Behalf Of
bbalend
Sent: Monday, April 18, 2005 11:08 AM
To: 68HC12@68HC...
Subject: [68HC12] Bootloader and Vector table.
Looks like my application require two vector table. one for application
and other one is for bootloader. There won't any sci interface
communication, except it will be present for debugging purpose. All
flash erase/programming are performed via the I2C bus.
So, my questions are:
1) Will there be any design issues that I have to watchout for?
2) How do switch/handle two vector table?
3) Which memory space is ideal for the two vector tables?
Note: Bootloader will only be program via the BDM.
Thanks _____
> .
[Non-text portions of this message have been removed]
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
I switched the compiler offset to place the application's vector tabel at
F7D0 and then placed the bootloader (with it's reset vector) at F800-FFFF.
There are a variety of ways that you can handle both interrupt vectors,
especially using program counter relative addressing. One way is to simply
point the bootloader's interrupt table vectors to a section of the
bootloader which will load X with an address that is some offset from the
current address, (which would be the application's corresponding interrupt
vector. Then once that address is loaded into X follow the command with a
JMP 0,X. this will set the PC to the address specified in the application's
vector table. The downside is that it adds about 4 or 5 clock cyles to the
interrupt latency, which often is not a big deal.
-Dave
_____
From: 68HC12@68HC... [mailto:68HC12@68HC...] On Behalf Of
bbalend
Sent: Monday, April 18, 2005 11:08 AM
To: 68HC12@68HC...
Subject: [68HC12] Bootloader and Vector table.
Looks like my application require two vector table. one for application
and other one is for bootloader. There won't any sci interface
communication, except it will be present for debugging purpose. All
flash erase/programming are performed via the I2C bus.
So, my questions are:
1) Will there be any design issues that I have to watchout for?
2) How do switch/handle two vector table?
3) Which memory space is ideal for the two vector tables?
Note: Bootloader will only be program via the BDM.
Thanks _____
> .
[Non-text portions of this message have been removed]
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Re: Bootloader and Vector table. - bbalend - Apr 20 14:38:00 2005
Hi David,
I am not quite following you. So can please you provide me a quick
example.
Here is a sample vector table for the bootloader.
/* Primary vector interrupt table will be used by the bootloader */
#define UnUsedVector (void (*)(void))0xFFFF
#pragma nonpaged_function ManagePower
ManagePower(void) {
...
}
#pragma abs_address:0xff88
void (*interrupt_vectors[])(void) = {
ManagePower, /* ff88 PWM - Emergency Shutdown */
UnusedVector, /* ff8A VREG LVI */
UnusedVector, /* ff8c PMF Fault 3 */
....
}
Thank you very much
Balend --- In 68HC12@68HC..., "David Wild" <david.wild@a...> wrote:
> In one case that I worked with the interrupt table normally started
at FFD0.
> I switched the compiler offset to place the application's vector
tabel at
> F7D0 and then placed the bootloader (with it's reset vector) at
F800-FFFF.
>
> There are a variety of ways that you can handle both interrupt
vectors,
> especially using program counter relative addressing. One way is to
simply
> point the bootloader's interrupt table vectors to a section of the
> bootloader which will load X with an address that is some offset
from the
> current address, (which would be the application's corresponding
interrupt
> vector. Then once that address is loaded into X follow the command
with a
> JMP 0,X. this will set the PC to the address specified in the
application's
> vector table. The downside is that it adds about 4 or 5 clock cyles
to the
> interrupt latency, which often is not a big deal.
>
> -Dave >
> _____
>
> From: 68HC12@68HC... [mailto:68HC12@68HC...] On
Behalf Of
> bbalend
> Sent: Monday, April 18, 2005 11:08 AM
> To: 68HC12@68HC...
> Subject: [68HC12] Bootloader and Vector table. >
> Looks like my application require two vector table. one for
application
> and other one is for bootloader. There won't any sci interface
> communication, except it will be present for debugging purpose.
All
> flash erase/programming are performed via the I2C bus.
>
> So, my questions are:
> 1) Will there be any design issues that I have to watchout for?
> 2) How do switch/handle two vector table?
> 3) Which memory space is ideal for the two vector tables?
>
> Note: Bootloader will only be program via the BDM.
>
> Thanks > _____
>
> > . >
>
> [Non-text portions of this message have been removed]
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Re: Bootloader and Vector table. - bbalend - Apr 21 8:58:00 2005
I got it!! Patrick Gempeler provided an example.
--- In 68HC12@68HC..., "bbalend" <bbalend@y...> wrote:
>
> Hi David,
>
> I am not quite following you. So can please you provide me a quick
> example.
>
> Here is a sample vector table for the bootloader.
>
> /* Primary vector interrupt table will be used by the bootloader */
>
> #define UnUsedVector (void (*)(void))0xFFFF
>
> #pragma nonpaged_function ManagePower
> ManagePower(void) {
> ...
> }
>
> #pragma abs_address:0xff88
> void (*interrupt_vectors[])(void) = {
>
> ManagePower, /* ff88 PWM - Emergency Shutdown */
> UnusedVector, /* ff8A VREG LVI */
> UnusedVector, /* ff8c PMF Fault 3 */
> ....
> }
>
> Thank you very much
> Balend > --- In 68HC12@68HC..., "David Wild" <david.wild@a...> wrote:
> > In one case that I worked with the interrupt table normally
started
> at FFD0.
> > I switched the compiler offset to place the application's vector
> tabel at
> > F7D0 and then placed the bootloader (with it's reset vector) at
> F800-FFFF.
> >
> > There are a variety of ways that you can handle both interrupt
> vectors,
> > especially using program counter relative addressing. One way is
to
> simply
> > point the bootloader's interrupt table vectors to a section of
the
> > bootloader which will load X with an address that is some offset
> from the
> > current address, (which would be the application's corresponding
> interrupt
> > vector. Then once that address is loaded into X follow the
command
> with a
> > JMP 0,X. this will set the PC to the address specified in the
> application's
> > vector table. The downside is that it adds about 4 or 5 clock
cyles
> to the
> > interrupt latency, which often is not a big deal.
> >
> > -Dave
> >
> >
> >
> > _____
> >
> > From: 68HC12@68HC... [mailto:68HC12@68HC...] On
> Behalf Of
> > bbalend
> > Sent: Monday, April 18, 2005 11:08 AM
> > To: 68HC12@68HC...
> > Subject: [68HC12] Bootloader and Vector table.
> >
> >
> >
> > Looks like my application require two vector table. one for
> application
> > and other one is for bootloader. There won't any sci interface
> > communication, except it will be present for debugging purpose.
> All
> > flash erase/programming are performed via the I2C bus.
> >
> > So, my questions are:
> > 1) Will there be any design issues that I have to watchout for?
> > 2) How do switch/handle two vector table?
> > 3) Which memory space is ideal for the two vector tables?
> >
> > Note: Bootloader will only be program via the BDM.
> >
> > Thanks
> >
> >
> >
> >
> >
> > _____
> >
> > > .
> >
> >
> >
> >
> > [Non-text portions of this message have been removed]
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
RE: Re: Bootloader and Vector table. - David Wild - Apr 21 10:44:00 2005
Excellent
Good luck with it. _____
From: 68HC12@68HC... [mailto:68HC12@68HC...] On Behalf Of
bbalend
Sent: Thursday, April 21, 2005 6:59 AM
To: 68HC12@68HC...
Subject: [68HC12] Re: Bootloader and Vector table.
I got it!! Patrick Gempeler provided an example.
--- In 68HC12@68HC..., "bbalend" <bbalend@y...> wrote:
>
> Hi David,
>
> I am not quite following you. So can please you provide me a quick
> example.
>
> Here is a sample vector table for the bootloader.
>
> /* Primary vector interrupt table will be used by the bootloader */
>
> #define UnUsedVector (void (*)(void))0xFFFF
>
> #pragma nonpaged_function ManagePower
> ManagePower(void) {
> ...
> }
>
> #pragma abs_address:0xff88
> void (*interrupt_vectors[])(void) = {
>
> ManagePower, /* ff88 PWM - Emergency Shutdown */
> UnusedVector, /* ff8A VREG LVI */
> UnusedVector, /* ff8c PMF Fault 3 */
> ....
> }
>
> Thank you very much
> Balend > --- In 68HC12@68HC..., "David Wild" <david.wild@a...> wrote:
> > In one case that I worked with the interrupt table normally
started
> at FFD0.
> > I switched the compiler offset to place the application's vector
> tabel at
> > F7D0 and then placed the bootloader (with it's reset vector) at
> F800-FFFF.
> >
> > There are a variety of ways that you can handle both interrupt
> vectors,
> > especially using program counter relative addressing. One way is
to
> simply
> > point the bootloader's interrupt table vectors to a section of
the
> > bootloader which will load X with an address that is some offset
> from the
> > current address, (which would be the application's corresponding
> interrupt
> > vector. Then once that address is loaded into X follow the
command
> with a
> > JMP 0,X. this will set the PC to the address specified in the
> application's
> > vector table. The downside is that it adds about 4 or 5 clock
cyles
> to the
> > interrupt latency, which often is not a big deal.
> >
> > -Dave
> >
> >
> >
> > _____
> >
> > From: 68HC12@68HC... [mailto:68HC12@68HC...] On
> Behalf Of
> > bbalend
> > Sent: Monday, April 18, 2005 11:08 AM
> > To: 68HC12@68HC...
> > Subject: [68HC12] Bootloader and Vector table.
> >
> >
> >
> > Looks like my application require two vector table. one for
> application
> > and other one is for bootloader. There won't any sci interface
> > communication, except it will be present for debugging purpose.
> All
> > flash erase/programming are performed via the I2C bus.
> >
> > So, my questions are:
> > 1) Will there be any design issues that I have to watchout for?
> > 2) How do switch/handle two vector table?
> > 3) Which memory space is ideal for the two vector tables?
> >
> > Note: Bootloader will only be program via the BDM.
> >
> > Thanks
> >
> >
> >
> >
> >
> > _____
> >
> > > .
> >
> >
> >
> >
> > [Non-text portions of this message have been removed] _____
> .
[Non-text portions of this message have been removed]
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Good luck with it. _____
From: 68HC12@68HC... [mailto:68HC12@68HC...] On Behalf Of
bbalend
Sent: Thursday, April 21, 2005 6:59 AM
To: 68HC12@68HC...
Subject: [68HC12] Re: Bootloader and Vector table.
I got it!! Patrick Gempeler provided an example.
--- In 68HC12@68HC..., "bbalend" <bbalend@y...> wrote:
>
> Hi David,
>
> I am not quite following you. So can please you provide me a quick
> example.
>
> Here is a sample vector table for the bootloader.
>
> /* Primary vector interrupt table will be used by the bootloader */
>
> #define UnUsedVector (void (*)(void))0xFFFF
>
> #pragma nonpaged_function ManagePower
> ManagePower(void) {
> ...
> }
>
> #pragma abs_address:0xff88
> void (*interrupt_vectors[])(void) = {
>
> ManagePower, /* ff88 PWM - Emergency Shutdown */
> UnusedVector, /* ff8A VREG LVI */
> UnusedVector, /* ff8c PMF Fault 3 */
> ....
> }
>
> Thank you very much
> Balend > --- In 68HC12@68HC..., "David Wild" <david.wild@a...> wrote:
> > In one case that I worked with the interrupt table normally
started
> at FFD0.
> > I switched the compiler offset to place the application's vector
> tabel at
> > F7D0 and then placed the bootloader (with it's reset vector) at
> F800-FFFF.
> >
> > There are a variety of ways that you can handle both interrupt
> vectors,
> > especially using program counter relative addressing. One way is
to
> simply
> > point the bootloader's interrupt table vectors to a section of
the
> > bootloader which will load X with an address that is some offset
> from the
> > current address, (which would be the application's corresponding
> interrupt
> > vector. Then once that address is loaded into X follow the
command
> with a
> > JMP 0,X. this will set the PC to the address specified in the
> application's
> > vector table. The downside is that it adds about 4 or 5 clock
cyles
> to the
> > interrupt latency, which often is not a big deal.
> >
> > -Dave
> >
> >
> >
> > _____
> >
> > From: 68HC12@68HC... [mailto:68HC12@68HC...] On
> Behalf Of
> > bbalend
> > Sent: Monday, April 18, 2005 11:08 AM
> > To: 68HC12@68HC...
> > Subject: [68HC12] Bootloader and Vector table.
> >
> >
> >
> > Looks like my application require two vector table. one for
> application
> > and other one is for bootloader. There won't any sci interface
> > communication, except it will be present for debugging purpose.
> All
> > flash erase/programming are performed via the I2C bus.
> >
> > So, my questions are:
> > 1) Will there be any design issues that I have to watchout for?
> > 2) How do switch/handle two vector table?
> > 3) Which memory space is ideal for the two vector tables?
> >
> > Note: Bootloader will only be program via the BDM.
> >
> > Thanks
> >
> >
> >
> >
> >
> > _____
> >
> > > .
> >
> >
> >
> >
> > [Non-text portions of this message have been removed] _____
> .
[Non-text portions of this message have been removed]
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )