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D60A clock issue (is it a Timer or PLL problem ?) - K.P.Venu - Nov 12 4:04:00 2002
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Hi All, I have strange problem related to D60A clock/Timer. While testing the system in the field our Test Engineer reported me that he has been getting poor performance. (There was a performance degradation around 50%.) Everything got all right when he restarted the system. From the field data I found that the Timer is running at 500Khz instead of 1Mhz. I'm using the Timer for all my system timing, capture/compare and other timing calculations. In my knowledge the only reason for this is corruption of Timer prescaler values in TMSK2 register. For a preventive measure, the s/w function Re_Init_All() updated with TMSK2 re-initialization value. ( Re_Init_All() used for refreshment of DDR values at every 1 second). But still I'm not sure that it's a Timer prescaler corruption or PLL Clock failure. I believe Fvcomin = 1Mhz (Limp-Home Mode) in the absence of external clock. Is there any chance to Limp-Home mode operating at 8Mhz. Is there any chance of corruption of SYNR and REFDV register. If yes, How do we correct that? If they're anybody experienced this kind of problems. Please help. Thanks in advance. Best Regards, Venu __________________________________________________ |
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Re: D60A clock issue (is it a Timer or PLL problem ?) - Ernst Darci-rzft50 - Nov 12 10:16:00 2002
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Venu, Which mask set are you using? If you are using the 2K38K, or the 0L51J mask set there is an errata on the limp home mode speed (AR636). The speed of those parts is about 3.5 MHz with a upper specification limit of 7.5 MHz. When you ask "Is there any chance to Limp-Home mode operating at 8Mhz" there is a chance it was as high as 7.5 MHz but that would be very rare. On a related note are you referring to bus speed? What is your crystal frequency? I assume you have Vddpll powered, is that correct? Were you starting and stopping the crystal in your test (either with the STOP instruction or power cycling)? I believe the only time you could have the SYNR or the REFDV being corrupted is when the BCSP = 0 (pll not running the bus clock). Regards, Darci -----Original Message----- From: K.P.Venu [mailto:] Sent: Tuesday, November 12, 2002 3:05 AM To: Subject: [68HC12] D60A clock issue (is it a Timer or PLL problem ?) Hi All, I have strange problem related to D60A clock/Timer. While testing the system in the field our Test Engineer reported me that he has been getting poor performance. (There was a performance degradation around 50%.) Everything got all right when he restarted the system. From the field data I found that the Timer is running at 500Khz instead of 1Mhz. I'm using the Timer for all my system timing, capture/compare and other timing calculations. In my knowledge the only reason for this is corruption of Timer prescaler values in TMSK2 register. For a preventive measure, the s/w function Re_Init_All() updated with TMSK2 re-initialization value. ( Re_Init_All() used for refreshment of DDR values at every 1 second). But still I'm not sure that it's a Timer prescaler corruption or PLL Clock failure. I believe Fvcomin = 1Mhz (Limp-Home Mode) in the absence of external clock. Is there any chance to Limp-Home mode operating at 8Mhz. Is there any chance of corruption of SYNR and REFDV register. If yes, How do we correct that? If they're anybody experienced this kind of problems. Please help. Thanks in advance. Best Regards, Venu __________________________________________________ -------------------- <http://www.motorola.com/mcu ">http://docs.yahoo.com/info/terms/> . |
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Re: D60A clock issue (is it a Timer or PLL problem ?) - K.P.Venu - Nov 12 23:16:00 2002
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Darci, I'm using 2K38K. My crystal frequency is 4Mhz and using PLL for an 8Mhz bus frequency. I 'm not stopping the crystal anywhere it's continues from Power ON. Regards, Venu --- Ernst Darci-rzft50 <> wrote: > Venu, > Which mask set are you using? If you are using > the 2K38K, or the 0L51J mask set there is an errata > on the limp home mode speed (AR636). The speed of > those parts is about 3.5 MHz with a upper > specification limit of 7.5 MHz. > > When you ask "Is there any chance to Limp-Home mode > operating > at 8Mhz" there is a chance it was as high as 7.5 MHz > but that would be very rare. On a related note are > you referring to bus speed? > > What is your crystal frequency? > I assume you have Vddpll powered, is that correct? > Were you starting and stopping the crystal in your > test (either with the STOP instruction or power > cycling)? > > I believe the only time you could have the SYNR > or the REFDV being corrupted is when the BCSP = 0 > (pll not running the bus clock). > > Regards, Darci > > -----Original Message----- > From: K.P.Venu [mailto:] > Sent: Tuesday, November 12, 2002 3:05 AM > To: > Subject: [68HC12] D60A clock issue (is it a Timer or > PLL problem ?) > __________________________________________________ |
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Re: D60A clock issue (is it a Timer or PLL problem ?) - Ernst Darci-rzft50 - Nov 13 11:57:00 2002
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Venu, My next questions would be was it possible you had the reported "slow" problem from power up or did it occur (change) while it was operating normally? With your set up you could easily get a 2 MHz bus (pll not switched to the bus), or if the crystal stopped I would expect the clock to be around 3 MHz (limp home mode). Can you tell any further information from when it acted up like was it running faster than 2 MHz? While the limp home speed will very from part to part and with temperature changes you can test your suspect part limp home mode speed and see what speed it runs. There are lots of other things like "What do you have in the PLLCR register?" since that has the limp home mode interrupt enable, PLL lock interrupt, etc.. Regards, Darci -----Original Message----- From: K.P.Venu [mailto:] Sent: Tuesday, November 12, 2002 10:16 PM To: Subject: RE: [68HC12] D60A clock issue (is it a Timer or PLL problem ?) Darci, I'm using 2K38K. My crystal frequency is 4Mhz and using PLL for an 8Mhz bus frequency. I 'm not stopping the crystal anywhere it's continues from Power ON. Regards, Venu |
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Re: D60A clock issue (is it a Timer or PLL problem ?) - K.P.Venu - Nov 14 10:00:00 2002
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Darci, The "slow problem" was present from Power ON itself. I'm not writing any thing to PLLCR, it's in the RESET state with PLLON bit set. (VDDPLL is high on power ON). One of my new findings is that the crystal was alive when the "slow" problem present. I'm using CAN and the CAN clock source is crystal clock (EXTALi).I do not found any problem with the control of actuators and internal data acquisition via CAN. From this I assumed that crystal is OK. There may be chance for a very long startup time but then How MSCAN was initialized/synchronized correctly? Darci, I'm listing my PLL clock settings and requirements please suggest me the right configuration of each PLL register. 1. crystal frequency = 4Mhz 2. Bus frequency = 8Mhz 3. XFC components = 12K, 220pF and 2.2nF 4. SYNR = 1 5. REFDV = 0 (using default value, not writing with 0) 6. No Limp Home Mode (NOLHM = 1) 7. Enable Clock monitor reset Startup code and PLL settings __stext: start: ldd #$00FF stab 0x02 ; configure PORTA as output staa 0x00 ; reset all port pins ldab #$01 ; Mult the reference by 4 (SYNCR value + 1). stab 0x38 ; kick up the PLL. nop ; nop ; relax for sometime nop ; nop ; brclr 0x3b,#$40,* ; wait here till the PLL is locked. bset 0x3c,#$01 ; remove limp-home mode bset 0x3d,#$40 ; switch the bus clock to the PLL. bset 0x16,#$40 ; enable Clock monitor reset lds #__stack ; initialize stack pointer // flash programming feature of ECU ldd _BootCode ; read Boot code cpd #$A55A ; Is there any BootCode present? beq LoadBoot ; Yes, Execute bootloader program jmp 0x1000 ; No, Execute ECU application s/w LoadBoot: jsr _LoadBootProgram; Fill internal RAM with BootLoader Program jmp 0x0200 ; execute BootLoader program from RAM end // end of startup code There is another problem when I try to re-initialize the TMSK2 register (to avoid timer prescaler corruption) at every 1 second. I'm getting wrong values in Timer2 capture input. The timer2 PERIOD is half for a given input frequency [T = 1 /(2*f)] and at the same time the other input capture channels are OK. (there is no s/w problem, frequency calculation function is common for all input channels). When I removed TMSK2 re-initialization, all capture channels are OK. Thanks and Best Regards, Venu --- Ernst Darci-rzft50 <> wrote: > Venu, > My next questions would be was it possible you > had the reported "slow" problem from power up or did > it occur (change) while it was operating normally? > With your set up you could easily get a 2 MHz > bus (pll not switched to the bus), or if the crystal > stopped I would expect the clock to be around 3 MHz > (limp home mode). Can you tell any further > information from when it acted up like was it > running faster than 2 MHz? While the limp home > speed will very from part to part and with > temperature changes you can test your suspect part > limp home mode speed and see what speed it runs. > There are lots of other things like "What do you > have in the PLLCR register?" since that has the limp > home mode interrupt enable, PLL lock interrupt, > etc.. > Regards, Darci __________________________________________________ |
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