68HC1 | 812A4 | 9S12DP256 | Bootloader | CodeWarrior | D60A | Debugger | DP256 | ECT | EEPROM | EVB | Flash | HC1 | HCS12 | I2C | IAR | ICC1 | Interrupts | LCD | M68KIT912DP256 | MC9S12DP256 | MC9S12DP256B | Metrowerks | Motor | MSCAN | Multilink | PLL | Quadrature | SDI | SPI | Transceiver | XFC

In an ISR, you have to either (a) make sure the ISR and all subroutines
that are called, are in unpaged flash, or (b), that the page register(s)
are restored at the end of the ISR. The same consideration applies for
RAM access, if you make any accesses to paged RAM areas, you must
restore the page register(s) at the end of the ISR. By experience, I
would suggest to do no paged accesses of any kind in ISR, that will also
help keep ISR execution time low.

Hope this helps. - I'm not sure if this is the cause of the problem that
you are experiencing, but it's a matter worth looking into.

Georg

________________________________

Von: 6...@yahoogroups.com [mailto:6...@yahoogroups.com] Im Auftrag
von joncas04
Gesendet: Freitag, 28. September 2007 11:33
An: 6...@yahoogroups.com
Betreff: [68HC12] procedure address alignment for HCS12

Hello Group,

i would be most grateful for advice on a strange issue:
when the code-length of a procedure that gets called from an interrupt
routine is odd, the program crashed when certain subroutines are called.
Adding an assignment like "var = 1;" to the routine to make its
code-length an even number of bytes, fixes the issue.
Is there some option flag or pragma statement one could add to make
the compiler or linker automatically make the code-length even?
This is a MC9S12DP256B processor with CodeWarrior 3.1

Many thanks in advance !
Robert

[Non-text portions of this message have been removed]



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