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S12DP256 ECT Problem - Adrian Vos - Nov 17 21:56:00 2002

Hi All,

I am having a very strange phenomona with the ECT in the DP256. I have got
the ECT set up with channels 0 and 1 as input capture, and I have a function
generator driving these pins togeather (so the interrupt occurs at as close
to the same point in time as possible). Anyway, this should generate an
interrupt on both channels, and it does, with channel 0 being of higher
priority, so serviced first. Anyway, the problem I am having is that when I
clear the flag for channel 0 by writing a 1 to the interrupt flag, it clears
the flag for channel 1 at the same time. As a result, no interrupt is
service on channel 1. I am writing my code in C with metrowerks, but have
dissassembled to be sure that I was not accidentally writing to the channel
1 flag. The dessasembled code uses a BSET TFLG1,#1. In my opinion, this
should not reult in writing a 1 to any bit other than bit 1, so should clear
only the channel 0 flag and not both?

I have checked the relevant registers to ensure I am not sharing the
channels togeather or anything, but I continue to get the problem. Has
anyone any suggestions on what my problem might be?

If I disconnect the function generator from channel 0, channel 1 works fine.
If I disable channel 0 interrupt, channel 1 works fine, so it is not
hardware problems in the signal getting to the pin. I have also put in some
debug code on either side of the flag clear to verify that the BSET is
clearing both flags, and this is definately the case.... I just don't get
it!!

Regards,

Adrian
----- Original Message -----
From: "iamuniqueandspecial" <>
To: <>
Sent: Saturday, November 16, 2002 1:42 PM
Subject: [68HC12] S12 crystal circuit design > I am having problems specifying a timing circuit for an S12; judging
> from the past list traffic, this is obviously a common problem since
> there is no reference design readily available.
>
> I understand the application-specific nature of circuits like this, so
> I would like to constuct a specific example that will meet my needs
> and hopefully those of others starting their learning curve. If I can
> get help with it and a reasonable assurance that it will work, I will
> test it and post a writeup on it in the common files section. All
> input is appreciated, especially analysis. I will test for basic
> parameters, but I do not have advanced testing equipment.
>
> This is being constructed for the MC9S12DJ256B 80 pin for small
> production (hand soldering) using components from Digikey, and should
> be applicable to most of the Star 12 processors based on the DP256B.
>
> So, here goes:
>
> Desired Performance:
>
> * OSCCLK of 10MHz, with at least %0.4 oscillator tollerance (4000 ppm)
> and 45%-55% duty cycle, as specified in the MSCAN Block Guide V02.14
> on page 59.
>
> * Bus Clock of 25MHz, using the PLL (core clock = 50MHz)
>
> * Begin executing application startup code in about 10ms
>
> * temperature range of about 0-70C > Hardware Implementation:
>
> > this is an implementation of Darci's earlier suggestion, with a
> 10MHz crystal simply substituted for the 4MHz crystal with capacitors
> chosen at the higher end of the recommended range. Note that C7 is
> from XTAL to ground, C8 is from EXTAL to XTAL, and C11 is Cdc
>
> > the PLL was selected using the S12 PLL Filter Calculator; R1 series
> resistance, C9 series capacitance, C10 parallel capacitance.
>
> * Layout specified in MC9S12DP256B Device User Guide -- V02.13 page
> 86, with power connected at VSSA and VDDA (as recommended).
> -Q1 Citizen 10MHz crystal, 18pF load capacitance, +-50ppm frequency
> tolerance, Digikey part 300-6121-1-ND
> -C1,C2,C3,C4,C5,C6 100nF 0805 ceramic X7R capacitor, Digikey part
> BC1300CT-ND
> -C7 22pF 0805 ceramic temperature compensated, Digikey part PCC220CNCT-ND
> -C8 33pF 0805 ceramic temperature compensated, Digikey part PCC330CGCT-ND
> -C9 4700pF 0805 ceramic X7R, Digikey part PCC2001CT-ND
> -C10 470pF 0805 ceramic temperature compensated, Digikey part
> PCC471CGCT-ND
> -C11 1800pF 0805 ceramic X7R, Digikey part PCC330CGCT-ND
> -R1 3.9K 0805 5% Digikey part P3.9KACT-ND
>
> * XCLKS tied to VDD
>
> * VRGEN tied to VDD > Software Implementation:
>
> * startup routine will be as follows:
> -REFDV = 1
> -SYNR = 4
> -loop while CRGFLG.LOCK == 0
> -CLKSEL.PLLSEL = 1
> -// application startup code >
> -Marcus Alexander > --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu http://www.sold.com.au - SOLD.com.au
- Find yourself a bargain!






(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )


Re: S12DP256 ECT Problem - kp_venu - Nov 17 23:46:00 2002

Adrian,
Do not use "BSET" instruction for clearing any interrupt flags.
If you use BSET instruction, it will first read TFLG1 register
and "OR this value with your "bit" and re-write it to TFLG1. So if
you are try to clear the timer0 flag it will clear timer1 flag also.
(if timer1 interrupt is pending).

Use TFLG1 = 0x01; and TFLG2 = 0x02; for clearing interrupt flags for
timer0 and timer1 respectively.

If you are a beginner I suggest you to read some "68HC12 programming"
books. Try this link for Jonathan W. Valvano's on-line book.
http://www.ece.utexas.edu/~valvano/embed/toc1.htm

Venu

--- In 68HC12@y..., "Adrian Vos" <vosadrian@y...> wrote:
> Hi All,
>
> I am having a very strange phenomona with the ECT in the DP256. I
have got
> the ECT set up with channels 0 and 1 as input capture, and I have a
function
> generator driving these pins togeather (so the interrupt occurs at
as close
> to the same point in time as possible). Anyway, this should
generate an
> interrupt on both channels, and it does, with channel 0 being of
higher
> priority, so serviced first. Anyway, the problem I am having is
that when I
> clear the flag for channel 0 by writing a 1 to the interrupt flag,
it clears
> the flag for channel 1 at the same time. As a result, no interrupt
is
> service on channel 1. I am writing my code in C with metrowerks,
but have
> dissassembled to be sure that I was not accidentally writing to the
channel
> 1 flag. The dessasembled code uses a BSET TFLG1,#1. In my opinion,
this
> should not reult in writing a 1 to any bit other than bit 1, so
should clear
> only the channel 0 flag and not both?
>
> I have checked the relevant registers to ensure I am not sharing the
> channels togeather or anything, but I continue to get the problem.
Has
> anyone any suggestions on what my problem might be?
>
> If I disconnect the function generator from channel 0, channel 1
works fine.
> If I disable channel 0 interrupt, channel 1 works fine, so it is not
> hardware problems in the signal getting to the pin. I have also put
in some
> debug code on either side of the flag clear to verify that the BSET
is
> clearing both flags, and this is definately the case.... I just
don't get
> it!!
>
> Regards,
>
> Adrian >
> ----- Original Message -----
> From: "iamuniqueandspecial" <iamuniqueandspecial@y...>
> To: <68HC12@y...>
> Sent: Saturday, November 16, 2002 1:42 PM
> Subject: [68HC12] S12 crystal circuit design > > I am having problems specifying a timing circuit for an S12;
judging
> > from the past list traffic, this is obviously a common problem
since
> > there is no reference design readily available.
> >
> > I understand the application-specific nature of circuits like
this, so
> > I would like to constuct a specific example that will meet my
needs
> > and hopefully those of others starting their learning curve. If
I can
> > get help with it and a reasonable assurance that it will work, I
will
> > test it and post a writeup on it in the common files section. All
> > input is appreciated, especially analysis. I will test for basic
> > parameters, but I do not have advanced testing equipment.
> >
> > This is being constructed for the MC9S12DJ256B 80 pin for small
> > production (hand soldering) using components from Digikey, and
should
> > be applicable to most of the Star 12 processors based on the
DP256B.
> >
> > So, here goes:
> >
> > Desired Performance:
> >
> > * OSCCLK of 10MHz, with at least %0.4 oscillator tollerance (4000
ppm)
> > and 45%-55% duty cycle, as specified in the MSCAN Block Guide
V02.14
> > on page 59.
> >
> > * Bus Clock of 25MHz, using the PLL (core clock = 50MHz)
> >
> > * Begin executing application startup code in about 10ms
> >
> > * temperature range of about 0-70C
> >
> >
> > Hardware Implementation:
> >
> > > this is an implementation of Darci's earlier suggestion, with a
> > 10MHz crystal simply substituted for the 4MHz crystal with
capacitors
> > chosen at the higher end of the recommended range. Note that C7
is
> > from XTAL to ground, C8 is from EXTAL to XTAL, and C11 is Cdc
> >
> > > the PLL was selected using the S12 PLL Filter Calculator; R1
series
> > resistance, C9 series capacitance, C10 parallel capacitance.
> >
> > * Layout specified in MC9S12DP256B Device User Guide -- V02.13
page
> > 86, with power connected at VSSA and VDDA (as recommended).
> > -Q1 Citizen 10MHz crystal, 18pF load capacitance, +-50ppm
frequency
> > tolerance, Digikey part 300-6121-1-ND
> > -C1,C2,C3,C4,C5,C6 100nF 0805 ceramic X7R capacitor, Digikey part
> > BC1300CT-ND
> > -C7 22pF 0805 ceramic temperature compensated, Digikey part
PCC220CNCT-ND
> > -C8 33pF 0805 ceramic temperature compensated, Digikey part
PCC330CGCT-ND
> > -C9 4700pF 0805 ceramic X7R, Digikey part PCC2001CT-ND
> > -C10 470pF 0805 ceramic temperature compensated, Digikey part
> > PCC471CGCT-ND
> > -C11 1800pF 0805 ceramic X7R, Digikey part PCC330CGCT-ND
> > -R1 3.9K 0805 5% Digikey part P3.9KACT-ND
> >
> > * XCLKS tied to VDD
> >
> > * VRGEN tied to VDD
> >
> >
> > Software Implementation:
> >
> > * startup routine will be as follows:
> > -REFDV = 1
> > -SYNR = 4
> > -loop while CRGFLG.LOCK == 0
> > -CLKSEL.PLLSEL = 1
> > -// application startup code
> >
> >
> >
> > -Marcus Alexander
> >
> >
> > --------------------------------------------------------
> > To unsubscribe from this group, send an email to:
> > 68HC12-unsubscribe@y...
> >
> > To learn more about Motorola Microcontrollers, please visit
> > http://www.motorola.com/mcu
> >
> >
> >
> >
>
> http://www.sold.com.au - SOLD.com.au
> - Find yourself a bargain!



(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )

Re: Re: S12DP256 ECT Problem - Adrian Vos - Nov 18 0:22:00 2002

Thanks Venu,

That seems to have fixed my problem.

I wouldn't have said I was a beginner, but this is my first HC(S)12 project.
I have previously used Metrowerks on HC08 and HC05 with success, as well as
assembly coding HC11, and various other non motorola devices. I have used
BSET and BCLR on the other platforms with no problems, and I am somewhat
surprised to have a problem here. I think the main difference I am
experiencing here is that with the HC08/05 you normally write a logic 0 to
clear a flag. Logically, this does not cause the same problem with a
BSET/BCLR, as if the flag is set, and you write a logic 1 back to it, it
will not be cleared. Because in HC12 the clears are normally done by writing
logic one, if a flag is set and you write it back to set, it is cleared.
Also, it is unusual in the other platforms to group multiple interrupt flags
in the same register which is the case in TFLG1.

Anyway, we live and learn!!

Thanks again!!

-- Adrian ----- Original Message -----
From: "kp_venu" <>
To: <>
Sent: Monday, November 18, 2002 3:46 PM
Subject: [68HC12] Re: S12DP256 ECT Problem > Adrian,
> Do not use "BSET" instruction for clearing any interrupt flags.
> If you use BSET instruction, it will first read TFLG1 register
> and "OR this value with your "bit" and re-write it to TFLG1. So if
> you are try to clear the timer0 flag it will clear timer1 flag also.
> (if timer1 interrupt is pending).
>
> Use TFLG1 = 0x01; and TFLG2 = 0x02; for clearing interrupt flags for
> timer0 and timer1 respectively.
>
> If you are a beginner I suggest you to read some "68HC12 programming"
> books. Try this link for Jonathan W. Valvano's on-line book.
> http://www.ece.utexas.edu/~valvano/embed/toc1.htm
>
> Venu
>
> --- In 68HC12@y..., "Adrian Vos" <vosadrian@y...> wrote:
> > Hi All,
> >
> > I am having a very strange phenomona with the ECT in the DP256. I
> have got
> > the ECT set up with channels 0 and 1 as input capture, and I have a
> function
> > generator driving these pins togeather (so the interrupt occurs at
> as close
> > to the same point in time as possible). Anyway, this should
> generate an
> > interrupt on both channels, and it does, with channel 0 being of
> higher
> > priority, so serviced first. Anyway, the problem I am having is
> that when I
> > clear the flag for channel 0 by writing a 1 to the interrupt flag,
> it clears
> > the flag for channel 1 at the same time. As a result, no interrupt
> is
> > service on channel 1. I am writing my code in C with metrowerks,
> but have
> > dissassembled to be sure that I was not accidentally writing to the
> channel
> > 1 flag. The dessasembled code uses a BSET TFLG1,#1. In my opinion,
> this
> > should not reult in writing a 1 to any bit other than bit 1, so
> should clear
> > only the channel 0 flag and not both?
> >
> > I have checked the relevant registers to ensure I am not sharing the
> > channels togeather or anything, but I continue to get the problem.
> Has
> > anyone any suggestions on what my problem might be?
> >
> > If I disconnect the function generator from channel 0, channel 1
> works fine.
> > If I disable channel 0 interrupt, channel 1 works fine, so it is not
> > hardware problems in the signal getting to the pin. I have also put
> in some
> > debug code on either side of the flag clear to verify that the BSET
> is
> > clearing both flags, and this is definately the case.... I just
> don't get
> > it!!
> >
> > Regards,
> >
> > Adrian
> >
> >
> >
> > ----- Original Message -----
> > From: "iamuniqueandspecial" <iamuniqueandspecial@y...>
> > To: <68HC12@y...>
> > Sent: Saturday, November 16, 2002 1:42 PM
> > Subject: [68HC12] S12 crystal circuit design
> >
> >
> > > I am having problems specifying a timing circuit for an S12;
> judging
> > > from the past list traffic, this is obviously a common problem
> since
> > > there is no reference design readily available.
> > >
> > > I understand the application-specific nature of circuits like
> this, so
> > > I would like to constuct a specific example that will meet my
> needs
> > > and hopefully those of others starting their learning curve. If
> I can
> > > get help with it and a reasonable assurance that it will work, I
> will
> > > test it and post a writeup on it in the common files section. All
> > > input is appreciated, especially analysis. I will test for basic
> > > parameters, but I do not have advanced testing equipment.
> > >
> > > This is being constructed for the MC9S12DJ256B 80 pin for small
> > > production (hand soldering) using components from Digikey, and
> should
> > > be applicable to most of the Star 12 processors based on the
> DP256B.
> > >
> > > So, here goes:
> > >
> > > Desired Performance:
> > >
> > > * OSCCLK of 10MHz, with at least %0.4 oscillator tollerance (4000
> ppm)
> > > and 45%-55% duty cycle, as specified in the MSCAN Block Guide
> V02.14
> > > on page 59.
> > >
> > > * Bus Clock of 25MHz, using the PLL (core clock = 50MHz)
> > >
> > > * Begin executing application startup code in about 10ms
> > >
> > > * temperature range of about 0-70C
> > >
> > >
> > > Hardware Implementation:
> > >
> > > > this is an implementation of Darci's earlier suggestion, with a
> > > 10MHz crystal simply substituted for the 4MHz crystal with
> capacitors
> > > chosen at the higher end of the recommended range. Note that C7
> is
> > > from XTAL to ground, C8 is from EXTAL to XTAL, and C11 is Cdc
> > >
> > > > the PLL was selected using the S12 PLL Filter Calculator; R1
> series
> > > resistance, C9 series capacitance, C10 parallel capacitance.
> > >
> > > * Layout specified in MC9S12DP256B Device User Guide -- V02.13
> page
> > > 86, with power connected at VSSA and VDDA (as recommended).
> > > -Q1 Citizen 10MHz crystal, 18pF load capacitance, +-50ppm
> frequency
> > > tolerance, Digikey part 300-6121-1-ND
> > > -C1,C2,C3,C4,C5,C6 100nF 0805 ceramic X7R capacitor, Digikey part
> > > BC1300CT-ND
> > > -C7 22pF 0805 ceramic temperature compensated, Digikey part
> PCC220CNCT-ND
> > > -C8 33pF 0805 ceramic temperature compensated, Digikey part
> PCC330CGCT-ND
> > > -C9 4700pF 0805 ceramic X7R, Digikey part PCC2001CT-ND
> > > -C10 470pF 0805 ceramic temperature compensated, Digikey part
> > > PCC471CGCT-ND
> > > -C11 1800pF 0805 ceramic X7R, Digikey part PCC330CGCT-ND
> > > -R1 3.9K 0805 5% Digikey part P3.9KACT-ND
> > >
> > > * XCLKS tied to VDD
> > >
> > > * VRGEN tied to VDD
> > >
> > >
> > > Software Implementation:
> > >
> > > * startup routine will be as follows:
> > > -REFDV = 1
> > > -SYNR = 4
> > > -loop while CRGFLG.LOCK == 0
> > > -CLKSEL.PLLSEL = 1
> > > -// application startup code
> > >
> > >
> > >
> > > -Marcus Alexander
> > >
> > >
> > > --------------------------------------------------------
> > > To unsubscribe from this group, send an email to:
> > > 68HC12-unsubscribe@y...
> > >
> > > To learn more about Motorola Microcontrollers, please visit
> > > http://www.motorola.com/mcu
> > >
> > >
> > >
> > >
> >
> > http://www.sold.com.au - SOLD.com.au
> > - Find yourself a bargain! > --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu http://careers.yahoo.com.au - Yahoo! Careers
- 1,000's of jobs waiting online for you!





(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )

Re: Re: S12DP256 ECT Problem - Edward Karpicz - Nov 18 3:57:00 2002

HC11 reference manual (pink book) , page 10-14:
Table 10-4. Instruction sequences to clear TOF (bit7 of
TFLG2)

1)
LDAA #$80
STAA TFLG2
2)
BCLR TFLG2 $7F

If C compiler uses BCLR/BSET instructions

TFLG2 &= ~0x80; or TFLG &= 0x7F;

Or
TFLG2 = 0x80; for ldaa+staa

Edward
----- Original Message -----
From: "Adrian Vos" <>
To: <>
Sent: Monday, November 18, 2002 7:22 AM
Subject: Re: [68HC12] Re: S12DP256 ECT Problem > Thanks Venu,
>
> That seems to have fixed my problem.
>
> I wouldn't have said I was a beginner, but this is my
first HC(S)12 project.
> I have previously used Metrowerks on HC08 and HC05 with
success, as well as
> assembly coding HC11, and various other non motorola
devices. I have used
> BSET and BCLR on the other platforms with no problems, and
I am somewhat
> surprised to have a problem here. I think the main
difference I am
> experiencing here is that with the HC08/05 you normally
write a logic 0 to
> clear a flag. Logically, this does not cause the same
problem with a
> BSET/BCLR, as if the flag is set, and you write a logic 1
back to it, it
> will not be cleared. Because in HC12 the clears are
normally done by writing
> logic one, if a flag is set and you write it back to set,
it is cleared.
> Also, it is unusual in the other platforms to group
multiple interrupt flags
> in the same register which is the case in TFLG1.
>
> Anyway, we live and learn!!
>
> Thanks again!!
>
> -- Adrian > ----- Original Message -----
> From: "kp_venu" <>
> To: <>
> Sent: Monday, November 18, 2002 3:46 PM
> Subject: [68HC12] Re: S12DP256 ECT Problem > > Adrian,
> > Do not use "BSET" instruction for clearing any interrupt
flags.
> > If you use BSET instruction, it will first read TFLG1
register
> > and "OR this value with your "bit" and re-write it to
TFLG1. So if
> > you are try to clear the timer0 flag it will clear
timer1 flag also.
> > (if timer1 interrupt is pending).
> >
> > Use TFLG1 = 0x01; and TFLG2 = 0x02; for clearing
interrupt flags for
> > timer0 and timer1 respectively.
> >
> > If you are a beginner I suggest you to read some "68HC12
programming"
> > books. Try this link for Jonathan W. Valvano's on-line
book.
> > http://www.ece.utexas.edu/~valvano/embed/toc1.htm
> >
> > Venu
> >
> > --- In 68HC12@y..., "Adrian Vos" <vosadrian@y...> wrote:
> > > Hi All,
> > >
> > > I am having a very strange phenomona with the ECT in
the DP256. I
> > have got
> > > the ECT set up with channels 0 and 1 as input capture,
and I have a
> > function
> > > generator driving these pins togeather (so the
interrupt occurs at
> > as close
> > > to the same point in time as possible). Anyway, this
should
> > generate an
> > > interrupt on both channels, and it does, with channel
0 being of
> > higher
> > > priority, so serviced first. Anyway, the problem I am
having is
> > that when I
> > > clear the flag for channel 0 by writing a 1 to the
interrupt flag,
> > it clears
> > > the flag for channel 1 at the same time. As a result,
no interrupt
> > is
> > > service on channel 1. I am writing my code in C with
metrowerks,
> > but have
> > > dissassembled to be sure that I was not accidentally
writing to the
> > channel
> > > 1 flag. The dessasembled code uses a BSET TFLG1,#1. In
my opinion,
> > this
> > > should not reult in writing a 1 to any bit other than
bit 1, so
> > should clear
> > > only the channel 0 flag and not both?
> > >
> > > I have checked the relevant registers to ensure I am
not sharing the
> > > channels togeather or anything, but I continue to get
the problem.
> > Has
> > > anyone any suggestions on what my problem might be?
> > >
> > > If I disconnect the function generator from channel 0,
channel 1
> > works fine.
> > > If I disable channel 0 interrupt, channel 1 works
fine, so it is not
> > > hardware problems in the signal getting to the pin. I
have also put
> > in some
> > > debug code on either side of the flag clear to verify
that the BSET
> > is
> > > clearing both flags, and this is definately the
case.... I just
> > don't get
> > > it!!
> > >
> > > Regards,
> > >
> > > Adrian
> > >
> > >
> > >
> > > ----- Original Message -----
> > > From: "iamuniqueandspecial" <iamuniqueandspecial@y...>
> > > To: <68HC12@y...>
> > > Sent: Saturday, November 16, 2002 1:42 PM
> > > Subject: [68HC12] S12 crystal circuit design
> > >
> > >
> > > > I am having problems specifying a timing circuit for
an S12;
> > judging
> > > > from the past list traffic, this is obviously a
common problem
> > since
> > > > there is no reference design readily available.
> > > >
> > > > I understand the application-specific nature of
circuits like
> > this, so
> > > > I would like to constuct a specific example that
will meet my
> > needs
> > > > and hopefully those of others starting their
learning curve. If
> > I can
> > > > get help with it and a reasonable assurance that it
will work, I
> > will
> > > > test it and post a writeup on it in the common files
section. All
> > > > input is appreciated, especially analysis. I will
test for basic
> > > > parameters, but I do not have advanced testing
equipment.
> > > >
> > > > This is being constructed for the MC9S12DJ256B 80
pin for small
> > > > production (hand soldering) using components from
Digikey, and
> > should
> > > > be applicable to most of the Star 12 processors
based on the
> > DP256B.
> > > >
> > > > So, here goes:
> > > >
> > > > Desired Performance:
> > > >
> > > > * OSCCLK of 10MHz, with at least %0.4 oscillator
tollerance (4000
> > ppm)
> > > > and 45%-55% duty cycle, as specified in the MSCAN
Block Guide
> > V02.14
> > > > on page 59.
> > > >
> > > > * Bus Clock of 25MHz, using the PLL (core clock =
50MHz)
> > > >
> > > > * Begin executing application startup code in about
10ms
> > > >
> > > > * temperature range of about 0-70C
> > > >
> > > >
> > > > Hardware Implementation:
> > > >
> > > > > this is an implementation of Darci's earlier
suggestion, with a
> > > > 10MHz crystal simply substituted for the 4MHz
crystal with
> > capacitors
> > > > chosen at the higher end of the recommended range.
Note that C7
> > is
> > > > from XTAL to ground, C8 is from EXTAL to XTAL, and
C11 is Cdc
> > > >
> > > > > the PLL was selected using the S12 PLL Filter
Calculator; R1
> > series
> > > > resistance, C9 series capacitance, C10 parallel
capacitance.
> > > >
> > > > * Layout specified in MC9S12DP256B Device User
Guide -- V02.13
> > page
> > > > 86, with power connected at VSSA and VDDA (as
recommended).
> > > > -Q1 Citizen 10MHz crystal, 18pF load capacitance,
+-50ppm
> > frequency
> > > > tolerance, Digikey part 300-6121-1-ND
> > > > -C1,C2,C3,C4,C5,C6 100nF 0805 ceramic X7R capacitor,
Digikey part
> > > > BC1300CT-ND
> > > > -C7 22pF 0805 ceramic temperature compensated,
Digikey part
> > PCC220CNCT-ND
> > > > -C8 33pF 0805 ceramic temperature compensated,
Digikey part
> > PCC330CGCT-ND
> > > > -C9 4700pF 0805 ceramic X7R, Digikey part
PCC2001CT-ND
> > > > -C10 470pF 0805 ceramic temperature compensated,
Digikey part
> > > > PCC471CGCT-ND
> > > > -C11 1800pF 0805 ceramic X7R, Digikey part
PCC330CGCT-ND
> > > > -R1 3.9K 0805 5% Digikey part P3.9KACT-ND
> > > >
> > > > * XCLKS tied to VDD
> > > >
> > > > * VRGEN tied to VDD
> > > >
> > > >
> > > > Software Implementation:
> > > >
> > > > * startup routine will be as follows:
> > > > -REFDV = 1
> > > > -SYNR = 4
> > > > -loop while CRGFLG.LOCK == 0
> > > > -CLKSEL.PLLSEL = 1
> > > > -// application startup code
> > > >
> > > >
> > > >
> > > > -Marcus Alexander
> > > >
> > > >
> > >
> --------------------------------------------------------
> > > > To unsubscribe from this group, send an email to:
> > > > 68HC12-unsubscribe@y...
> > > >
> > > > To learn more about Motorola Microcontrollers,
please visit
> > > > http://www.motorola.com/mcu
> > > >
> > > >
> > > >
> > > >
> > >
> > > http://www.sold.com.au - SOLD.com.au
> > > - Find yourself a bargain!
> >
> >
> > --------------------------------------------------------
> > To unsubscribe from this group, send an email to:
> >
> >
> > To learn more about Motorola Microcontrollers, please
visit
> > http://www.motorola.com/mcu
> >
> >
> >
> >
>
> http://careers.yahoo.com.au - Yahoo! Careers
> - 1,000's of jobs waiting online for you!
>
> ------------------------ Yahoo! Groups
Sponsor ---------------------~-->
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visit
> http://www.motorola.com/mcu





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Re: Re: S12DP256 ECT Problem - Robert Smith - Nov 18 5:49:00 2002

This is a well known "problem" with the 'HC11. It sounds like the 'HC12
uses the same timer module as the '11 which is not unexpected in this family
of modular Motorola MCUs.

Since you have 'HC11 background, dig out your Pink Book and read Section
10.2.4, "Tips for clearing Timer Flags" for a thorough discussion of this
"problem". Among other things, it will teach you how to use the BCLR
instruction to accomplish this function without unintentionally clearing
other than the desired interrupt.

Good luck, Bob Smith --- Avoid computer viruses, Practice safe hex ---

-- Specializing in small, cost effective
embedded control systems -- Robert L. (Bob) Smith
Smith Machine Works, Inc.
9900 Lumlay Road
Richmond, VA 23236 804/745-1065
----- Original Message -----
From: "Adrian Vos" <>
To: <>
Sent: Monday, November 18, 2002 12:22 AM
Subject: Re: [68HC12] Re: S12DP256 ECT Problem > Thanks Venu,
>
> That seems to have fixed my problem.
>
> I wouldn't have said I was a beginner, but this is my first HC(S)12
project.
> I have previously used Metrowerks on HC08 and HC05 with success, as well
as
> assembly coding HC11, and various other non motorola devices. I have used
> BSET and BCLR on the other platforms with no problems, and I am somewhat
> surprised to have a problem here. I think the main difference I am
> experiencing here is that with the HC08/05 you normally write a logic 0 to
> clear a flag. Logically, this does not cause the same problem with a
> BSET/BCLR, as if the flag is set, and you write a logic 1 back to it, it
> will not be cleared. Because in HC12 the clears are normally done by
writing
> logic one, if a flag is set and you write it back to set, it is cleared.
> Also, it is unusual in the other platforms to group multiple interrupt
flags
> in the same register which is the case in TFLG1.
>
> Anyway, we live and learn!!
>
> Thanks again!!
>
> -- Adrian > ----- Original Message -----
> From: "kp_venu" <>
> To: <>
> Sent: Monday, November 18, 2002 3:46 PM
> Subject: [68HC12] Re: S12DP256 ECT Problem > > Adrian,
> > Do not use "BSET" instruction for clearing any interrupt flags.
> > If you use BSET instruction, it will first read TFLG1 register
> > and "OR this value with your "bit" and re-write it to TFLG1. So if
> > you are try to clear the timer0 flag it will clear timer1 flag also.
> > (if timer1 interrupt is pending).
> >
> > Use TFLG1 = 0x01; and TFLG2 = 0x02; for clearing interrupt flags for
> > timer0 and timer1 respectively.
> >
> > If you are a beginner I suggest you to read some "68HC12 programming"
> > books. Try this link for Jonathan W. Valvano's on-line book.
> > http://www.ece.utexas.edu/~valvano/embed/toc1.htm
> >
> > Venu
> >
> > --- In 68HC12@y..., "Adrian Vos" <vosadrian@y...> wrote:
> > > Hi All,
> > >
> > > I am having a very strange phenomona with the ECT in the DP256. I
> > have got
> > > the ECT set up with channels 0 and 1 as input capture, and I have a
> > function
> > > generator driving these pins togeather (so the interrupt occurs at
> > as close
> > > to the same point in time as possible). Anyway, this should
> > generate an
> > > interrupt on both channels, and it does, with channel 0 being of
> > higher
> > > priority, so serviced first. Anyway, the problem I am having is
> > that when I
> > > clear the flag for channel 0 by writing a 1 to the interrupt flag,
> > it clears
> > > the flag for channel 1 at the same time. As a result, no interrupt
> > is
> > > service on channel 1. I am writing my code in C with metrowerks,
> > but have
> > > dissassembled to be sure that I was not accidentally writing to the
> > channel
> > > 1 flag. The dessasembled code uses a BSET TFLG1,#1. In my opinion,
> > this
> > > should not reult in writing a 1 to any bit other than bit 1, so
> > should clear
> > > only the channel 0 flag and not both?
> > >
> > > I have checked the relevant registers to ensure I am not sharing the
> > > channels togeather or anything, but I continue to get the problem.
> > Has
> > > anyone any suggestions on what my problem might be?
> > >
> > > If I disconnect the function generator from channel 0, channel 1
> > works fine.
> > > If I disable channel 0 interrupt, channel 1 works fine, so it is not
> > > hardware problems in the signal getting to the pin. I have also put
> > in some
> > > debug code on either side of the flag clear to verify that the BSET
> > is
> > > clearing both flags, and this is definately the case.... I just
> > don't get
> > > it!!
> > >
> > > Regards,
> > >
> > > Adrian
> > >
> > >
> > >
> > > ----- Original Message -----
> > > From: "iamuniqueandspecial" <iamuniqueandspecial@y...>
> > > To: <68HC12@y...>
> > > Sent: Saturday, November 16, 2002 1:42 PM
> > > Subject: [68HC12] S12 crystal circuit design
> > >
> > >
> > > > I am having problems specifying a timing circuit for an S12;
> > judging
> > > > from the past list traffic, this is obviously a common problem
> > since
> > > > there is no reference design readily available.
> > > >
> > > > I understand the application-specific nature of circuits like
> > this, so
> > > > I would like to constuct a specific example that will meet my
> > needs
> > > > and hopefully those of others starting their learning curve. If
> > I can
> > > > get help with it and a reasonable assurance that it will work, I
> > will
> > > > test it and post a writeup on it in the common files section. All
> > > > input is appreciated, especially analysis. I will test for basic
> > > > parameters, but I do not have advanced testing equipment.
> > > >
> > > > This is being constructed for the MC9S12DJ256B 80 pin for small
> > > > production (hand soldering) using components from Digikey, and
> > should
> > > > be applicable to most of the Star 12 processors based on the
> > DP256B.
> > > >
> > > > So, here goes:
> > > >
> > > > Desired Performance:
> > > >
> > > > * OSCCLK of 10MHz, with at least %0.4 oscillator tollerance (4000
> > ppm)
> > > > and 45%-55% duty cycle, as specified in the MSCAN Block Guide
> > V02.14
> > > > on page 59.
> > > >
> > > > * Bus Clock of 25MHz, using the PLL (core clock = 50MHz)
> > > >
> > > > * Begin executing application startup code in about 10ms
> > > >
> > > > * temperature range of about 0-70C
> > > >
> > > >
> > > > Hardware Implementation:
> > > >
> > > > > this is an implementation of Darci's earlier suggestion, with a
> > > > 10MHz crystal simply substituted for the 4MHz crystal with
> > capacitors
> > > > chosen at the higher end of the recommended range. Note that C7
> > is
> > > > from XTAL to ground, C8 is from EXTAL to XTAL, and C11 is Cdc
> > > >
> > > > > the PLL was selected using the S12 PLL Filter Calculator; R1
> > series
> > > > resistance, C9 series capacitance, C10 parallel capacitance.
> > > >
> > > > * Layout specified in MC9S12DP256B Device User Guide -- V02.13
> > page
> > > > 86, with power connected at VSSA and VDDA (as recommended).
> > > > -Q1 Citizen 10MHz crystal, 18pF load capacitance, +-50ppm
> > frequency
> > > > tolerance, Digikey part 300-6121-1-ND
> > > > -C1,C2,C3,C4,C5,C6 100nF 0805 ceramic X7R capacitor, Digikey part
> > > > BC1300CT-ND
> > > > -C7 22pF 0805 ceramic temperature compensated, Digikey part
> > PCC220CNCT-ND
> > > > -C8 33pF 0805 ceramic temperature compensated, Digikey part
> > PCC330CGCT-ND
> > > > -C9 4700pF 0805 ceramic X7R, Digikey part PCC2001CT-ND
> > > > -C10 470pF 0805 ceramic temperature compensated, Digikey part
> > > > PCC471CGCT-ND
> > > > -C11 1800pF 0805 ceramic X7R, Digikey part PCC330CGCT-ND
> > > > -R1 3.9K 0805 5% Digikey part P3.9KACT-ND
> > > >
> > > > * XCLKS tied to VDD
> > > >
> > > > * VRGEN tied to VDD
> > > >
> > > >
> > > > Software Implementation:
> > > >
> > > > * startup routine will be as follows:
> > > > -REFDV = 1
> > > > -SYNR = 4
> > > > -loop while CRGFLG.LOCK == 0
> > > > -CLKSEL.PLLSEL = 1
> > > > -// application startup code
> > > >
> > > >
> > > >
> > > > -Marcus Alexander
> > > >
> > > >
> > > > --------------------------------------------------------
> > > > To unsubscribe from this group, send an email to:
> > > > 68HC12-unsubscribe@y...
> > > >
> > > > To learn more about Motorola Microcontrollers, please visit
> > > > http://www.motorola.com/mcu
> > > >
> > > >
> > > >
> > > >
> > >
> > > http://www.sold.com.au - SOLD.com.au
> > > - Find yourself a bargain!
> >
> >
> > --------------------------------------------------------
> > To unsubscribe from this group, send an email to:
> >
> >
> > To learn more about Motorola Microcontrollers, please visit
> > http://www.motorola.com/mcu
> >
> >
> >
> >
>
> http://careers.yahoo.com.au - Yahoo! Careers
> - 1,000's of jobs waiting online for you! > --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu




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Surplus D60A 112-pin available - James M. Knox - Nov 18 9:35:00 2002


I have 16 parts left over, still in waffle packs, of the KMC912D60ACPV8
(that's the 112 pin package) that I don't currently need. I don't know
what these are going for in small qty (i.e. less than the usual 84 part
packages), but if anyone needs them it is better than letting them sit
around here.

jmk

-----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1109-A Shady Lane fax 512-366-4331
Austin, Tx 78721
-----------------------------------------------



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