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Discussion Groups | 68HC12 | Instruction trace buffer
Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).
Instruction trace buffer - Robert Milne - Apr 23 9:07:33 2008
I have an unexplained intermittant reset that is defying my crude
debugging methods (sci print statements and pod breakpoints) and I
need a more sophisticated tool to trace the source of the problem.
The Techarts bdm (xg) I own is useless with noice when the pll is
active, but even with a more capable pod I'm unsure whether an
affordable instruction trace buffer is available. Can anyone suggest
a solution?
-rob
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
debugging methods (sci print statements and pod breakpoints) and I
need a more sophisticated tool to trace the source of the problem.
The Techarts bdm (xg) I own is useless with noice when the pll is
active, but even with a more capable pod I'm unsure whether an
affordable instruction trace buffer is available. Can anyone suggest
a solution?
-rob
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Re: Instruction trace buffer - Edward Karpicz - Apr 23 10:14:08 2008
Robert,
what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
families only. But even if you have onchip trace buffer, I'm not sure if
tracing over reset is possible. I've tried enabling and reading trace buffer
myself and came to the impression tracing over reset is not possible, reset
must be ressitting way too much. I would like to hear I'm wrong and tracing
over reset is possible...
Regards
Edward
Robert Milne wrote:
>I have an unexplained intermittant reset that is defying my crude
> debugging methods (sci print statements and pod breakpoints) and I
> need a more sophisticated tool to trace the source of the problem.
> The Techarts bdm (xg) I own is useless with noice when the pll is
> active, but even with a more capable pod I'm unsure whether an
> affordable instruction trace buffer is available. Can anyone suggest
> a solution?
>
> -rob
>
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
families only. But even if you have onchip trace buffer, I'm not sure if
tracing over reset is possible. I've tried enabling and reading trace buffer
myself and came to the impression tracing over reset is not possible, reset
must be ressitting way too much. I would like to hear I'm wrong and tracing
over reset is possible...
Regards
Edward
Robert Milne wrote:
>I have an unexplained intermittant reset that is defying my crude
> debugging methods (sci print statements and pod breakpoints) and I
> need a more sophisticated tool to trace the source of the problem.
> The Techarts bdm (xg) I own is useless with noice when the pll is
> active, but even with a more capable pod I'm unsure whether an
> affordable instruction trace buffer is available. Can anyone suggest
> a solution?
>
> -rob
>
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Re: Instruction trace buffer - Rob Milne - Apr 23 11:26:59 2008
Hi Edward,
I'm using the 48 pin 9S12C32 and 64 with ICC12V7. I know a trace would
be possible via the 80 pin chip with IPIPE lines and a logic analyser.
I'm really fishing here, but would it be possible for write the
instruction queue to a ring buffer in RAM that is continually
overwritten and then view this area after reset? If this buffer region
is between __bss_end and the expected bottom of the stack I could avoid
the zero init on _start.
-rob
Edward Karpicz wrote:
> Robert,
>
> what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
> families only. But even if you have onchip trace buffer, I'm not sure if
> tracing over reset is possible. I've tried enabling and reading trace
> buffer
> myself and came to the impression tracing over reset is not possible, reset
> must be ressitting way too much. I would like to hear I'm wrong and tracing
> over reset is possible...
>
> Regards
> Edward
>
> Robert Milne wrote:
>
> >I have an unexplained intermittant reset that is defying my crude
> > debugging methods (sci print statements and pod breakpoints) and I
> > need a more sophisticated tool to trace the source of the problem.
> > The Techarts bdm (xg) I own is useless with noice when the pll is
> > active, but even with a more capable pod I'm unsure whether an
> > affordable instruction trace buffer is available. Can anyone suggest
> > a solution?
> >
> > -rob
> >
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
I'm using the 48 pin 9S12C32 and 64 with ICC12V7. I know a trace would
be possible via the 80 pin chip with IPIPE lines and a logic analyser.
I'm really fishing here, but would it be possible for write the
instruction queue to a ring buffer in RAM that is continually
overwritten and then view this area after reset? If this buffer region
is between __bss_end and the expected bottom of the stack I could avoid
the zero init on _start.
-rob
Edward Karpicz wrote:
> Robert,
>
> what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
> families only. But even if you have onchip trace buffer, I'm not sure if
> tracing over reset is possible. I've tried enabling and reading trace
> buffer
> myself and came to the impression tracing over reset is not possible, reset
> must be ressitting way too much. I would like to hear I'm wrong and tracing
> over reset is possible...
>
> Regards
> Edward
>
> Robert Milne wrote:
>
> >I have an unexplained intermittant reset that is defying my crude
> > debugging methods (sci print statements and pod breakpoints) and I
> > need a more sophisticated tool to trace the source of the problem.
> > The Techarts bdm (xg) I own is useless with noice when the pll is
> > active, but even with a more capable pod I'm unsure whether an
> > affordable instruction trace buffer is available. Can anyone suggest
> > a solution?
> >
> > -rob
> >
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Re: Instruction trace buffer - Rob Milne - Apr 23 12:04:00 2008
I wrote a quick test to see if data written between __bss_end and the
stack remains unaltered after a COP reset (no power cycling) and indeed
it is stable. Does anyone know a way to place instruction queue data
into RAM?
-rob
Rob Milne wrote:
> Hi Edward,
>
> I'm using the 48 pin 9S12C32 and 64 with ICC12V7. I know a trace would
> be possible via the 80 pin chip with IPIPE lines and a logic analyser.
>
> I'm really fishing here, but would it be possible for write the
> instruction queue to a ring buffer in RAM that is continually
> overwritten and then view this area after reset? If this buffer region
> is between __bss_end and the expected bottom of the stack I could avoid
> the zero init on _start.
>
> -rob
>
> Edward Karpicz wrote:
> >
> >
> > Robert,
> >
> > what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
> > families only. But even if you have onchip trace buffer, I'm not sure if
> > tracing over reset is possible. I've tried enabling and reading trace
> > buffer
> > myself and came to the impression tracing over reset is not possible,
> reset
> > must be ressitting way too much. I would like to hear I'm wrong and
> tracing
> > over reset is possible...
> >
> > Regards
> > Edward
> >
> > Robert Milne wrote:
> >
> > >I have an unexplained intermittant reset that is defying my crude
> > > debugging methods (sci print statements and pod breakpoints) and I
> > > need a more sophisticated tool to trace the source of the problem.
> > > The Techarts bdm (xg) I own is useless with noice when the pll is
> > > active, but even with a more capable pod I'm unsure whether an
> > > affordable instruction trace buffer is available. Can anyone suggest
> > > a solution?
> > >
> > > -rob
> > >
> >
> >
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
stack remains unaltered after a COP reset (no power cycling) and indeed
it is stable. Does anyone know a way to place instruction queue data
into RAM?
-rob
Rob Milne wrote:
> Hi Edward,
>
> I'm using the 48 pin 9S12C32 and 64 with ICC12V7. I know a trace would
> be possible via the 80 pin chip with IPIPE lines and a logic analyser.
>
> I'm really fishing here, but would it be possible for write the
> instruction queue to a ring buffer in RAM that is continually
> overwritten and then view this area after reset? If this buffer region
> is between __bss_end and the expected bottom of the stack I could avoid
> the zero init on _start.
>
> -rob
>
> Edward Karpicz wrote:
> >
> >
> > Robert,
> >
> > what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
> > families only. But even if you have onchip trace buffer, I'm not sure if
> > tracing over reset is possible. I've tried enabling and reading trace
> > buffer
> > myself and came to the impression tracing over reset is not possible,
> reset
> > must be ressitting way too much. I would like to hear I'm wrong and
> tracing
> > over reset is possible...
> >
> > Regards
> > Edward
> >
> > Robert Milne wrote:
> >
> > >I have an unexplained intermittant reset that is defying my crude
> > > debugging methods (sci print statements and pod breakpoints) and I
> > > need a more sophisticated tool to trace the source of the problem.
> > > The Techarts bdm (xg) I own is useless with noice when the pll is
> > > active, but even with a more capable pod I'm unsure whether an
> > > affordable instruction trace buffer is available. Can anyone suggest
> > > a solution?
> > >
> > > -rob
> > >
> >
> >
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Re: Instruction trace buffer - Edward Karpicz - Apr 23 13:24:08 2008
Rob,
> Hi Edward,
>
> I'm using the 48 pin 9S12C32 and 64 with ICC12V7. I know a trace would
> be possible via the 80 pin chip with IPIPE lines and a logic analyser.
You are talking about chip emulator, like those available from www.Nohau.com
>
> I'm really fishing here, but would it be possible for write the
> instruction queue to a ring buffer in RAM that is continually
> overwritten and then view this area after reset? If this buffer region
> is between __bss_end and the expected bottom of the stack I could avoid
> the zero init on _start.
S12C Debug module has onchip trace buffer. Trace buffer can record vew
program steps. Check Debug Module Block Description chapter for more
details. I don't know if onchip trace buffer can help you
Edward
>
> -rob
>
> Edward Karpicz wrote:
>> Robert,
>>
>> what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
>> families only. But even if you have onchip trace buffer, I'm not sure if
>> tracing over reset is possible. I've tried enabling and reading trace
>> buffer
>> myself and came to the impression tracing over reset is not possible,
>> reset
>> must be ressitting way too much. I would like to hear I'm wrong and
>> tracing
>> over reset is possible...
>>
>> Regards
>> Edward
>>
>> Robert Milne wrote:
>>
>> >I have an unexplained intermittant reset that is defying my crude
>> > debugging methods (sci print statements and pod breakpoints) and I
>> > need a more sophisticated tool to trace the source of the problem.
>> > The Techarts bdm (xg) I own is useless with noice when the pll is
>> > active, but even with a more capable pod I'm unsure whether an
>> > affordable instruction trace buffer is available. Can anyone suggest
>> > a solution?
>> >
>> > -rob
>> >
>>
>> ------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
> Hi Edward,
>
> I'm using the 48 pin 9S12C32 and 64 with ICC12V7. I know a trace would
> be possible via the 80 pin chip with IPIPE lines and a logic analyser.
You are talking about chip emulator, like those available from www.Nohau.com
>
> I'm really fishing here, but would it be possible for write the
> instruction queue to a ring buffer in RAM that is continually
> overwritten and then view this area after reset? If this buffer region
> is between __bss_end and the expected bottom of the stack I could avoid
> the zero init on _start.
S12C Debug module has onchip trace buffer. Trace buffer can record vew
program steps. Check Debug Module Block Description chapter for more
details. I don't know if onchip trace buffer can help you
Edward
>
> -rob
>
> Edward Karpicz wrote:
>> Robert,
>>
>> what MCU you are using? AFAIK trace buffer is available in S12C and S12Xx
>> families only. But even if you have onchip trace buffer, I'm not sure if
>> tracing over reset is possible. I've tried enabling and reading trace
>> buffer
>> myself and came to the impression tracing over reset is not possible,
>> reset
>> must be ressitting way too much. I would like to hear I'm wrong and
>> tracing
>> over reset is possible...
>>
>> Regards
>> Edward
>>
>> Robert Milne wrote:
>>
>> >I have an unexplained intermittant reset that is defying my crude
>> > debugging methods (sci print statements and pod breakpoints) and I
>> > need a more sophisticated tool to trace the source of the problem.
>> > The Techarts bdm (xg) I own is useless with noice when the pll is
>> > active, but even with a more capable pod I'm unsure whether an
>> > affordable instruction trace buffer is available. Can anyone suggest
>> > a solution?
>> >
>> > -rob
>> >
>>
>> ------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
Port input impedance - "James M. Knox" - Apr 23 16:47:25 2008
Here's a bit of a strange question that does not seem to be in the
data book. Does anyone know the input impedance of the standard
S12Axx ports (A, B, etc.) when the chip is OFF (no Vdd)?
I've got a power supply design (multiple inputs) that is driving me
bonkers because of some bizarre requirements. I've got most of that
fixed, but I have to be careful about off-state current drain and
also letting any voltage reach the input ports (can cause reset
problems on power up). So I need to pull up a high-side FET with
something like a 1 MEG resistor, but this is also accessed through a
diode to an S12 input port. I've done this okay with a 10K pullup -
but is the port impedance when the IC is off going to drag down the 1
meg pullup?
The data book gives the 5V leakage into the ports when on as between
10 and 130 uAmps (pullup/pulldown enabled). But no spec with it off!
Ideas...
tnx, jmk
-----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1300 Koenig Lane West fax 512-371-5716
Suite 200
Austin, Tx 78756 j...@trisoft.com
-----------------------------------------------
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
RE: Port input impedance - Anders Friberg - Apr 23 18:11:26 2008
> -----Original Message-----
> From: 6...@yahoogroups.com [mailto:6...@yahoogroups.com]
> On Behalf Of James M. Knox
> Sent: Wednesday, April 23, 2008 10:47 PM
> To: 6...@yahoogroups.com
> Subject: [68HC12] Port input impedance
> Here's a bit of a strange question that does not seem to be in the
> data book. Does anyone know the input impedance of the standard
> S12Axx ports (A, B, etc.) when the chip is OFF (no Vdd)?
>
I/O pins of an unpowered chip will probably act like shorted to GND with a
diode (if the i/o pin has the protection reverse diode to VCC and this is
normally the case). To have circuits "disconnected" from the chip when not
powered normally means some extra open collector driver or similar next to
the chip.
Regards,
Anders
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
> From: 6...@yahoogroups.com [mailto:6...@yahoogroups.com]
> On Behalf Of James M. Knox
> Sent: Wednesday, April 23, 2008 10:47 PM
> To: 6...@yahoogroups.com
> Subject: [68HC12] Port input impedance
> Here's a bit of a strange question that does not seem to be in the
> data book. Does anyone know the input impedance of the standard
> S12Axx ports (A, B, etc.) when the chip is OFF (no Vdd)?
>
I/O pins of an unpowered chip will probably act like shorted to GND with a
diode (if the i/o pin has the protection reverse diode to VCC and this is
normally the case). To have circuits "disconnected" from the chip when not
powered normally means some extra open collector driver or similar next to
the chip.
Regards,
Anders
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
RE: Port input impedance - "James M. Knox" - Apr 24 9:22:10 2008
At 00:11 4/24/2008 +0200, you wrote:
> >
> > Here's a bit of a strange question that does not seem to be in the
> > data book. Does anyone know the input impedance of the standard
> > S12Axx ports (A, B, etc.) when the chip is OFF (no Vdd)?
> >I/O pins of an unpowered chip will probably act like shorted to GND with a
>diode (if the i/o pin has the protection reverse diode to VCC and this is
>normally the case). To have circuits "disconnected" from the chip when not
>powered normally means some extra open collector driver or similar next to
>the chip.
Thanks... sounds like I need some more blocking diodes and FETs...
Dang, this circuit is getting very complicated to do something very
simple.
jmk
-----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1300 Koenig Lane West fax 512-371-5716
Suite 200
Austin, Tx 78756 j...@trisoft.com
-----------------------------------------------
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )
> >
> > Here's a bit of a strange question that does not seem to be in the
> > data book. Does anyone know the input impedance of the standard
> > S12Axx ports (A, B, etc.) when the chip is OFF (no Vdd)?
> >I/O pins of an unpowered chip will probably act like shorted to GND with a
>diode (if the i/o pin has the protection reverse diode to VCC and this is
>normally the case). To have circuits "disconnected" from the chip when not
>powered normally means some extra open collector driver or similar next to
>the chip.
Thanks... sounds like I need some more blocking diodes and FETs...
Dang, this circuit is getting very complicated to do something very
simple.
jmk
-----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1300 Koenig Lane West fax 512-371-5716
Suite 200
Austin, Tx 78756 j...@trisoft.com
-----------------------------------------------
------------------------------------
(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )