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Discussion Groups | 68HC12 | BIG Question: Crystal Clock Generation on 9S12DP256

Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).

RE: BIG Question: Crystal Clock Generation on 9S12DP256 - James M. Knox - May 7 5:09:00 2003

At 10:18 PM 5/7/2003 +0100, you wrote:

>*** Please accept the following as the definitive statement on this issue ***
>"To save cost, my customer wants to drive the S12 with an existing 5 volt
>crystal module, but I'm certain that the external clock should be at the
>VddPLL level, not 5volt.

Admittedly, I am working with D60A's, not S12's, but I've got VddPLL tied
to ground (as was my understanding of a valid configuration for an external
clock input). Does this mean that I need to keep my external clock signal
at zero volts? <G>

Seriously, seems to be a conflict here. And I still can't find anything in
the datasheet that even hints at this. Where am I missing it?

jmk -----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1109-A Shady Lane fax 512-366-4331
Austin, Tx 78721
-----------------------------------------------



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BIG Question: Crystal Clock Generation on 9S12DP256 - Steve Gordon - May 7 10:18:00 2003

Hello All:

This message is for Gordon D. (and to all) who can provide a brief response
to confirm the requirements on the clock section of the newer HCS family
devices.

Is it a requirement to provide a 2.5 volt signaling level clock signal to
the HCS devices?

I can tell that it works at 5V with no apparent issues.

How critical is the level of the clock signal with respect to signal
integrity inside the HCS12 parts?

I need to know if external 5V to 2.5V circuitry is not just a
recommendation, but a strict requirement in the evolution these processors?

If anybody knows the true gospel on this question, please drop us all a
line, if for nothing other than peace of mind regarding this important
specification.

Thanks to all in advance.

Steven R. Gordon
Hardware Engineer
New Product Division

Moore Industries International
The Interface Solution Experts
16650 Schoenborn Street
North Hills, CA 91343-6196
Phone: (818) 891 - 2816
Fax: (818) 891 - 2816
Email:
Website: www.miinet.com
-----Original Message-----
From: James M. Knox [mailto:]
Sent: Tuesday, May 06, 2003 7:25 PM
To:
Subject: Re: [68HC12] Trouble With Crystal Clock Generation on 9S12DP256

At 05:11 PM 5/2/2003 +0200, you wrote:

>2. Use an external clock generator.
>The external clock generator also has several possible complications that
>need to be taken care of:
>It requires a square wave voltage levels of 0V and 2.5V which requires also
>a 2.5V external voltage regulator on your board.

Is that 2.5V restriction unique to the 9S12DP256? I looked at other
datasheets (like the D60A) and it looks like a 5V drive signal (basically,
anything up to Vdd) is fine.

jmk
-----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1109-A Shady Lane fax 512-366-4331
Austin, Tx 78721
-----------------------------------------------
--------------------------------------------------------
To unsubscribe from this group, send an email to: To learn more about Motorola Microcontrollers, please visit
http://www.motorola.com/mcu






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Re: BIG Question: Crystal Clock Generation on 9S12DP256 - Pat Fitzpatrick - May 7 12:52:00 2003

Somebody at Motorola (I forget who) told me that running the clock at 5 volts
will damage the part -- though I too ran one at 5 volts (albeit with a series
resistor) for quite a while with no observable problems. Maybe it will kill the
processor over time. I sure wouldn't risk it.

We just use a voltage divider on the output of the oscillator and it seems to
work fine. Just make sure both resistors are installed or you, too, may find
your clock running at 5 volts after all.

Pat

Steve Gordon wrote:

> Hello All:
>
> This message is for Gordon D. (and to all) who can provide a brief response
> to confirm the requirements on the clock section of the newer HCS family
> devices.
>
> Is it a requirement to provide a 2.5 volt signaling level clock signal to
> the HCS devices?
>
> I can tell that it works at 5V with no apparent issues.
>
> How critical is the level of the clock signal with respect to signal
> integrity inside the HCS12 parts?
>
> I need to know if external 5V to 2.5V circuitry is not just a
> recommendation, but a strict requirement in the evolution these processors?
>
> If anybody knows the true gospel on this question, please drop us all a
> line, if for nothing other than peace of mind regarding this important
> specification.
>
> Thanks to all in advance.
>
> Steven R. Gordon
> Hardware Engineer
> New Product Division
>
> Moore Industries International
> The Interface Solution Experts
> 16650 Schoenborn Street
> North Hills, CA 91343-6196
> Phone: (818) 891 - 2816
> Fax: (818) 891 - 2816
> Email:
> Website: www.miinet.com >
> -----Original Message-----
> From: James M. Knox [mailto:]
> Sent: Tuesday, May 06, 2003 7:25 PM
> To:
> Subject: Re: [68HC12] Trouble With Crystal Clock Generation on 9S12DP256
>
> At 05:11 PM 5/2/2003 +0200, you wrote:
>
> >2. Use an external clock generator.
> >The external clock generator also has several possible complications that
> >need to be taken care of:
> >It requires a square wave voltage levels of 0V and 2.5V which requires also
> >a 2.5V external voltage regulator on your board.
>
> Is that 2.5V restriction unique to the 9S12DP256? I looked at other
> datasheets (like the D60A) and it looks like a 5V drive signal (basically,
> anything up to Vdd) is fine.
>
> jmk
>
> -----------------------------------------------
> James M. Knox
> TriSoft ph 512-385-0316
> 1109-A Shady Lane fax 512-366-4331
> Austin, Tx 78721
> -----------------------------------------------
>
> --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu > --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu



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RE: BIG Question: Crystal Clock Generation on 9S12DP256 - Dunnett Mark-R60287 - May 7 16:18:00 2003

Hello Group,

As a Motorola FAE I have seen the question about using an external clock on S12 devices a number of times. I checked with my colleagues at TSPG Applications Engineering in the factory the first time it cropped up.

*** Please accept the following as the definitive statement on this issue ***
"To save cost, my customer wants to drive the S12 with an existing 5 volt crystal module, but I'm certain that the external clock should be at the VddPLL level, not 5volt.

1) Please confirm that the external clock source should be at VddPLL.
Answer: Yes, the external clock source should be at the VddPLL voltage.

2) Any special things to take into consideration... obviously XTAL no connect, XCLKS asserted, XFC to VddPLL, signal in on EXTAL.
Answer: XTAL = No connect, XCLKS = ground (select external clock), XFC via 1 to 5k resistor to VddPll (never to VssPll!), clock into EXTAL.

3) If customer needs to generate 2.5 volt buffer, how much current can he pull from VddPLL? I guess he'd need a simple transistor buffer in emitter-follower configuration
Answer: There is a much simpler way - use a simple resistor potential divider. It is cheaper, uses no active components and takes seconds to assemble.
The VddPll pin, like the Vdd1 and Vdd2 pins are intended for providing a method of attaching external decoupling, they are NOT intended for drawing current from the MCU. This is likely to cause internal damage to the MCU and obviously we would not recommend this."

This information applies to all 5 volt variants of the S12. KR,

Mark

The information contained in this communication has been classified as:
(X) General Business Information
( ) Motorola & Distributor Internal Use Only
( ) Motorola Confidential Proprietary
-----Original Message-----
From: Pat Fitzpatrick [mailto:]
Sent: 07 May 2003 18:53
To:
Subject: Re: [68HC12] BIG Question: Crystal Clock Generation on 9S12DP256 Somebody at Motorola (I forget who) told me that running the clock at 5 volts
will damage the part -- though I too ran one at 5 volts (albeit with a series
resistor) for quite a while with no observable problems. Maybe it will kill the
processor over time. I sure wouldn't risk it.

We just use a voltage divider on the output of the oscillator and it seems to
work fine. Just make sure both resistors are installed or you, too, may find
your clock running at 5 volts after all.

Pat

Steve Gordon wrote:

> Hello All:
>
> This message is for Gordon D. (and to all) who can provide a brief response
> to confirm the requirements on the clock section of the newer HCS family
> devices.
>
> Is it a requirement to provide a 2.5 volt signaling level clock signal to
> the HCS devices?
>
> I can tell that it works at 5V with no apparent issues.
>
> How critical is the level of the clock signal with respect to signal
> integrity inside the HCS12 parts?
>
> I need to know if external 5V to 2.5V circuitry is not just a
> recommendation, but a strict requirement in the evolution these processors?
>
> If anybody knows the true gospel on this question, please drop us all a
> line, if for nothing other than peace of mind regarding this important
> specification.
>
> Thanks to all in advance.
>
> Steven R. Gordon
> Hardware Engineer
> New Product Division
>
> Moore Industries International
> The Interface Solution Experts
> 16650 Schoenborn Street
> North Hills, CA 91343-6196
> Phone: (818) 891 - 2816
> Fax: (818) 891 - 2816
> Email:
> Website: www.miinet.com >
> -----Original Message-----
> From: James M. Knox [mailto:]
> Sent: Tuesday, May 06, 2003 7:25 PM
> To:
> Subject: Re: [68HC12] Trouble With Crystal Clock Generation on 9S12DP256
>
> At 05:11 PM 5/2/2003 +0200, you wrote:
>
> >2. Use an external clock generator.
> >The external clock generator also has several possible complications that
> >need to be taken care of:
> >It requires a square wave voltage levels of 0V and 2.5V which requires also
> >a 2.5V external voltage regulator on your board.
>
> Is that 2.5V restriction unique to the 9S12DP256? I looked at other
> datasheets (like the D60A) and it looks like a 5V drive signal (basically,
> anything up to Vdd) is fine.
>
> jmk
>
> -----------------------------------------------
> James M. Knox
> TriSoft ph 512-385-0316
> 1109-A Shady Lane fax 512-366-4331
> Austin, Tx 78721
> -----------------------------------------------
>
> --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu <http://www.motorola.com/mcu > <http://docs.yahoo.com/info/terms/ > --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu <http://www.motorola.com/mcu > <http://docs.yahoo.com/info/terms/
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--------------------------------------------------------
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RE: BIG Question: Crystal Clock Generation on 9S12DP256 - Dunnett Mark-R60287 - May 8 3:38:00 2003

HI,

Yes, there are differences between HC12 and S12, most notably the voltage regulator on the S12.

With the HC12, if the PLL is not being used, the VddPLL is recommended to be held at Vss. [Reference MC68HC912D60/D Rev 3 July 2002 page 43, Section 4.3.5]

With the S12, the pins VddPLL and VssPLL have different function - they are ***OUTPUTS*** from the internal voltage regulator [sorry for the shouting]. The intention of these pins is to allow decoupling of the PLL supply [it is not practical to implement supply decoupling on-silicon].

The tables for the supply pins in the device user guide 9S12DP256BDGV2/D shows VddPLL as 2.5 volts. Section 4.2.1 of the CRG Block User Guide states that the oscillator is powered from VddPLL. Result? An external clock input to S12's should be at 2.5 volt levels. I didn't check forthcoming (unreleased) S12 devices, since these are not generally available to this forum yet.

BUT.... if VREGEN is tied Low, then the voltage regulator is disabled and the supplies must be provided by the user, and the VddPLL (etc) becomes an input.

KR,

Mark

The information contained in this communication has been classified as:
(X) General Business Information
( ) Motorola & Distributor Internal Use Only
( ) Motorola Confidential Proprietary

-----Original Message-----
From: James M. Knox [mailto:]
Sent: 07 May 2003 11:10
To:
Subject: RE: [68HC12] BIG Question: Crystal Clock Generation on 9S12DP256 At 10:18 PM 5/7/2003 +0100, you wrote:

>*** Please accept the following as the definitive statement on this issue ***
>"To save cost, my customer wants to drive the S12 with an existing 5 volt
>crystal module, but I'm certain that the external clock should be at the
>VddPLL level, not 5volt.

Admittedly, I am working with D60A's, not S12's, but I've got VddPLL tied
to ground (as was my understanding of a valid configuration for an external
clock input). Does this mean that I need to keep my external clock signal
at zero volts? <G>

Seriously, seems to be a conflict here. And I still can't find anything in
the datasheet that even hints at this. Where am I missing it?

jmk -----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1109-A Shady Lane fax 512-366-4331
Austin, Tx 78721
-----------------------------------------------
Yahoo! Groups Sponsor
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<http://us.adserver.yahoo.com/l?M=251812.3170658.4537139.1261774/D=egroupmail/S=:HM/A=1564416/rand=531847049>

--------------------------------------------------------
To unsubscribe from this group, send an email to: To learn more about Motorola Microcontrollers, please visit
http://www.motorola.com/mcu <http://www.motorola.com/mcu > .
[Non-text portions of this message have been removed]



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RE: BIG Question: Crystal Clock Generation on 9S12DP256 - James M. Knox - May 8 8:34:00 2003

At 09:38 AM 5/8/2003 +0100, you wrote:
>
>With the S12, the pins VddPLL and VssPLL have different function - they
>are ***OUTPUTS*** from the internal voltage regulator [sorry for the
>shouting]. The intention of these pins is to allow decoupling of the PLL
>supply

Don't worry about the shouting. Sometimes it takes a little "specific
clarification" (read: 2 x 4 up side the head) to make sure I get the
message. <G>

Thanks for the info...
jmk -----------------------------------------------
James M. Knox
TriSoft ph 512-385-0316
1109-A Shady Lane fax 512-366-4331
Austin, Tx 78721
-----------------------------------------------



(You need to be a member of 68hc12 -- send a blank email to 68hc12-subscribe@yahoogroups.com )