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Discussion Groups | 68HC12 | How about nested(multiplined?) interrupts in HSC12 ?

Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).

How about nested(multiplined?) interrupts in HSC12 ? - lenux22 - May 26 10:43:00 2003


Hello!
I had a question about interrupts organisation in HCS12.
If interrupt routine for low-priority interrupt is curently execute and new interrupt with high-priority is come, which one would execute?
If first service rounting doesn't interrupted until it done, how i can
interrupt it? Maybe NMI (XIRQ) can interrupt interrupt's handler?
Am i right? Please let me know...

WBR, lenux





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Re: How about nested(multiplined?) interrupts in HSC12 ? - Doron Fael - May 26 14:54:00 2003

Hello,

When an ISR (interrupt service routine) is starting to execute, the I bit
in the CCR register is set automatically to disable recognition of more
interrupts. When the RTI instruction is used to end the ISR and return, the
CCR register is restored from the stack, and the I bit is again cleared to
enable interrupts.

If you would like to enable interrupts to be recognized within the ISR, use
the CLI instruction (ANDCC #$EF) to clear the I bit, and enable more
interrupts to be recognized within the executed ISR.

The priority of the interrupts is set according to descending order of the
interrupt vector addresses.
On HCS12 parts, it is possible to promote one single interrupt source to
have the highest priority by writing the LSB address of the appropriate
interrupt vector to the HPRIO register.
The interrupt priority has meaning only when two or more interrupt requests
are being processed at the same time to determine which ISR will be
executed first. Once a certain ISR has started to execute, the interrupt
priority has no relevancy to determine if another interrupt can interrupt
the already executing ISR or not. This aspect is handled by the CCR
register I bit, as explained above.

Hope this helps,

Doron
Nohau Corporation
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html

At 03:43 PM 5/26/2003 +0000, you wrote:

>Hello!
>I had a question about interrupts organisation in HCS12.
>If interrupt routine for low-priority interrupt is curently execute and
>new interrupt with high-priority is come, which one would execute?
>If first service rounting doesn't interrupted until it done, how i can
>interrupt it? Maybe NMI (XIRQ) can interrupt interrupt's handler?
>Am i right? Please let me know...
>
>WBR, lenux
[Non-text portions of this message have been removed]




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Re: How about nested(multiplined?) interrupts in HSC12 ? - lenux22 - May 27 2:38:00 2003

Hi!
Thanks for good explanation.
Let me ask you one more question about HCS12 interrupts.
It's about XIRQ (Non maskable interrupts). If ISR for common (maskable) interrupt is currently executed, and MNI is come, do HCS12 leave current ISR and start ISR for NMI, then done ISR for NMI it's return for old ISR and done it? I know about X bit. Common interrupts doesn't touch with bit. So, I think NMI is enable during other ISRs.
Is it so?

WBR, lenux

--- In , Doron Fael <doronf@n...> wrote:
> Hello,
>
> When an ISR (interrupt service routine) is starting to execute, the I bit
> in the CCR register is set automatically to disable recognition of more
> interrupts. When the RTI instruction is used to end the ISR and return, the
> CCR register is restored from the stack, and the I bit is again cleared to
> enable interrupts.
>
> If you would like to enable interrupts to be recognized within the ISR, use
> the CLI instruction (ANDCC #$EF) to clear the I bit, and enable more
> interrupts to be recognized within the executed ISR.
>
> The priority of the interrupts is set according to descending order of the
> interrupt vector addresses.
> On HCS12 parts, it is possible to promote one single interrupt source to
> have the highest priority by writing the LSB address of the appropriate
> interrupt vector to the HPRIO register.
> The interrupt priority has meaning only when two or more interrupt requests
> are being processed at the same time to determine which ISR will be
> executed first. Once a certain ISR has started to execute, the interrupt
> priority has no relevancy to determine if another interrupt can interrupt
> the already executing ISR or not. This aspect is handled by the CCR
> register I bit, as explained above.
>
> Hope this helps,
>
> Doron
> Nohau Corporation
> HC12 In-Circuit Emulators
> www.nohau.com/emul12pc.html



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Re: Re: How about nested(multiplined?) interrupts in HSC12 ? - Andrew Lohmann's New Email Server - May 27 2:55:00 2003

What you are asking for is what my HD6301 application has been doing for
years. I am converting that application to HCS12.

NMI will interrupt an interrupt. In other words NMI or XIRQ is nestable as
you suggest, the only difference over NMI is that XIRQ needs to be enabled.

Now if you were to want to change priorities of interrupts, allow some
higher level interrupts to interrupt lower level interrupts, have a look at
HC16. HC16's interrupt handling is very elegant, and powerful, but at the
same time not difficult to understand. Andrew Lohmann AIIE
Design Engineer

Bellingham + Stanley Ltd.
Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England.
Tel: +44 (0) 1892 500400
Fax: +44 (0) 1892 543115
Website: www.bs-ltd.com
----- Original Message -----
From: "lenux22" <>
To: <>
Sent: Tuesday, May 27, 2003 8:38 AM
Subject: [68HC12] Re: How about nested(multiplined?) interrupts in HSC12 ? > Hi!
> Thanks for good explanation.
> Let me ask you one more question about HCS12 interrupts.
> It's about XIRQ (Non maskable interrupts). If ISR for common (maskable)
interrupt is currently executed, and MNI is come, do HCS12 leave current ISR
and start ISR for NMI, then done ISR for NMI it's return for old ISR and
done it? I know about X bit. Common interrupts doesn't touch with bit. So,
I think NMI is enable during other ISRs.
> Is it so?
>
> WBR, lenux
>
> --- In , Doron Fael <doronf@n...> wrote:
> > Hello,
> >
> > When an ISR (interrupt service routine) is starting to execute, the I
bit
> > in the CCR register is set automatically to disable recognition of more
> > interrupts. When the RTI instruction is used to end the ISR and return,
the
> > CCR register is restored from the stack, and the I bit is again cleared
to
> > enable interrupts.
> >
> > If you would like to enable interrupts to be recognized within the ISR,
use
> > the CLI instruction (ANDCC #$EF) to clear the I bit, and enable more
> > interrupts to be recognized within the executed ISR.
> >
> > The priority of the interrupts is set according to descending order of
the
> > interrupt vector addresses.
> > On HCS12 parts, it is possible to promote one single interrupt source to
> > have the highest priority by writing the LSB address of the appropriate
> > interrupt vector to the HPRIO register.
> > The interrupt priority has meaning only when two or more interrupt
requests
> > are being processed at the same time to determine which ISR will be
> > executed first. Once a certain ISR has started to execute, the interrupt
> > priority has no relevancy to determine if another interrupt can
interrupt
> > the already executing ISR or not. This aspect is handled by the CCR
> > register I bit, as explained above.
> >
> > Hope this helps,
> >
> > Doron
> > Nohau Corporation
> > HC12 In-Circuit Emulators
> > www.nohau.com/emul12pc.html
> > --------------------------------------------------------
> To unsubscribe from this group, send an email to: > To learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu >
>
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