Re: pll D60C and D60P availability? | 68HC12

Oliver It appears as though you are suggesting that in ANY harsh environment the PLL is necessary for the D60a. So, for my application, using an 8Mhz crystal (and thus a 4 mhz bus speed) to duplicate this using a PLL I would need to let SYNC=0 and REFDIV=1. Of course, this is purely academic since our boards are already designed without the PLL, but for future reference....the S12 PLL filter calculator program yields series resistance=820 ohm series capacitance=33nf parallel capacitance=3.3 nf will these values work for the D60a as well? I can't seem to find a calculator program for the D60a. Stewart Prince Professor, Mech Eng CSUN Oliver Betz wrote: >James M. Knox wrote: > >>>>I thought the PLL wouldn't let you run at 16 MHz on the D60A. Obviously I >>>> >>>> >>>The max. bus clock is 8MHz, with or without the PLL. >>> >>> >>Okay... poor choice of words. I thought the max clock (not E-clock) speed >>with crystal or resonator for the 60A was only 8 - 10 MHz. Whereas with an >> >> > >Therefore I suggested to use a 8MHz crystal and the PLL (to get 8MHz >E clock). > >BTW: Although the docs suggest not to use the PLL clock for CAN >because it could have too much jitter, I don't believe that this >warning is well-founded. CAN is quite robust against small amounts of >jitter, and my own jitter measurements showed no alarming deviation, >you should find my mail about this in the group archive. > >BTW2: I wouldn't use a slower crystal because the BDM starts with >this frequency, and many BDM interfaces are not able to use the PLL. > >Oliver [Non-text portions of this message have been removed]

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Stewart Prince wrote: > It appears as though you are suggesting that in ANY harsh environment > the PLL is necessary for the D60a. So, for my application, using an if "harsh" means that transients (ESD, EFT) can hit the board: yes. Indirect ESD caused "code runaway" with external 8MHz crystal and without PLL. With PLL no problems (unshielded device). > 8Mhz crystal (and thus a 4 mhz bus speed) to duplicate this using a PLL > I would need to let SYNC=0 and REFDIV=1. Of course, this is purely I use SYNR = 0 (*1) and REFDV = 0 (/1) - the nominal PLL frequency is the bus clock, not twice the bus clock as the crystal is. > academic since our boards are already designed without the PLL, but for > future reference....the S12 PLL filter calculator program yields > series resistance=820 ohm > series capacitance=33nf > parallel capacitance=3.3 nf I think the S12 values are not applicable because the S12 VCO has (to have) a higher frequency coefficient. The D60 docs list some exampe components, and have (IIRC) some errors. There are some mails from me in the list archives regarding this. > will these values work for the D60a as well? I can't seem to find a > calculator program for the D60a. I use 1nF, 10nF, 5kOhms but don't use these values without own checks. Oliver -- Oliver Betz, Muenchen

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Discussion Groups | 68HC12 | Re: pll D60C and D60P availability?

Re: pll D60C and D60P availability? - Stewart Prince - Dec 4 23:59:00 2003

Re: pll D60C and D60P availability? - Oliver Betz - Dec 5 13:13:00 2003