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Discussion Groups | 68HC12 | Clock oscillator question
Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).
Clock oscillator question - Steve-HighPoint - Mar 24 14:38:00 2004
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I am working on a project using either the 9s12A256 or the DP256 part. I have on my
board a clock oscillator running at 5VDC and using two 10K resistors to divide the voltage
to be compatible with the processor clock input. 1.. My prototype uses a 16Mhz clock and works fine. My IAR CSpy was limited to this frequency and I was successful with my development. I now need to go to the full 48 Mhz speed the processor is capable of. 2.. I have started using the PE Micro debugger which will work at 48Mhz clock input. 3.. My question is - should I use a 48 Mhz clock oscillator with the resistor divider or stick to 16Mhz and use the PLL to step up to 48 Mhz? 4.. My preference is to use the 48Mhz clock oscillator and not populate the PLL filter. 5.. Does anyone have any experience with this? Thanks in advance for your help in this matter. Regards, Steve Dillier HighPoint Technology LLC [Non-text portions of this message have been removed] |
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Re: Clock oscillator question - Andrew Lohmann's New Email Server - Mar 25 3:48:00 2004
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Although the P&E multilink12 is only rated at 35MHz, this is the core speed, not
the normally quoted bus speed. I have briefly and reliably used parallel multilink 12 with
MC9S12DP256 at 50MHz core clock, (normally described as 25MHz bus). The Colpits Oscillators, which should be the most susceptible, seems more tolerant of supply noise than the PLL, but they work well. It follows that an external oscillator would be more stable, but you will have too look at the data sheet see what the maximum frequency can be. Andrew Lohmann AIIE Design Engineer PLEASE NOTE NEW EMAIL ADDRESS IS: Bellingham + Stanley Ltd. Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England. Tel: +44 (0) 1892 500400 Fax: +44 (0) 1892 543115 Website: www.bs-ltd.com ----- Original Message ----- From: Steve-HighPoint To: Sent: Wednesday, March 24, 2004 7:38 PM Subject: [68HC12] Clock oscillator question I am working on a project using either the 9s12A256 or the DP256 part. I have on my board a clock oscillator running at 5VDC and using two 10K resistors to divide the voltage to be compatible with the processor clock input. 1.. My prototype uses a 16Mhz clock and works fine. My IAR CSpy was limited to this frequency and I was successful with my development. I now need to go to the full 48 Mhz speed the processor is capable of. 2.. I have started using the PE Micro debugger which will work at 48Mhz clock input. 3.. My question is - should I use a 48 Mhz clock oscillator with the resistor divider or stick to 16Mhz and use the PLL to step up to 48 Mhz? 4.. My preference is to use the 48Mhz clock oscillator and not populate the PLL filter. 5.. Does anyone have any experience with this? Thanks in advance for your help in this matter. Regards, Steve Dillier HighPoint Technology LLC [Non-text portions of this message have been removed] --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu o learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu Yahoo! Groups Sponsor ADVERTISEMENT ------------------------------------------------------------------------------ Yahoo! Groups Links a.. To [Non-text portions of this message have been removed] |
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Re: Clock oscillator question - Doron Fael - Mar 25 4:23:00 2004
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Steve, The DP256 data sheets specify that when supplying 50MHz clock-generator signal with 2.5V voltage swing to the EXTAL pin, the rise time and fall time need to be no more than 0.5nSEC (the clock high and clock low time are required to be at least 9.5nSEC). My experience is that at room temperature this works, even with 1nSEC rise and fall time, but you might not want to risk it if your design needs to be tested at the temperature extremes and work even with both slow and normal silicon. With a voltage divider made of two 10K resistors (like used by your lower speed application), you need to also take into account a 5 - 10 pF capacitance on the EXTAL input. The effect of the capacitance and the two 10K resistors is long rise and fall times on the EXTAL input - on the order of no less than 5Kohm * 5pF = 25 nSEC - this is very far from the specified maximum of 0.5nSEC in the DP256 data sheets! Even if you reduce the resistors to 470ohm (which will increase the current consumption from your clock generator significantly), you will still have a time constant of no less than 1.25nSEC. Still marginal in my opinion - but might be operable - I am not sure. Another possibility, if you insist on using a clock generator, and supply 48MHz, is to use a Pericom 74ST1G125 buffer, powered by 2.5V, to buffer between your 5V clock generator, and the DP256 EXTAL input. This solution too has a draw-back: In Stop power-down mode the VDD and VDDPLL voltages generated internally in the DP256 may drop significantly to about 1.6V. If in this case, you continue to feed a 2.5V Clock to the EXTAL input, you may damage the DP256 device. The solution to this draw-back is either not use the STOP power-down mode, or connect Schottky (low voltage) diodes between your external 2.5V supply and the VDD and VDDPLL pins, so the external diodes pull the VDD and VDDPLL high when the internal voltage regulator drops the voltage. (this solution was offered to me by the Motorola HCS12 design team - so I am pretty sure it is safe to use). Then, after all the above discussion, I believe it would be easier for you to use a lower frequency crystal or clock generator, and then use the internal DP256 PLL to up the bus speed to the 24MHz you require. The internal HCS12 PLL is pretty good, and most applications I am aware of use it. In my opinion, you should consider not using the internal PLL only if your application 1) Requires a fast start-up after Reset with the final frequency (since the PLL takes time to lock), or 2) Your application requires very high frequency stability and low jitter, and cannot withstand the higher jitter and lower frequency stability of a PLL circuit. Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 13:38 24/03/2004 -0600, you wrote: >I am working on a project using either the 9s12A256 or the DP256 part. I >have on my board a clock oscillator running at 5VDC and using two 10K >resistors to divide the voltage to be compatible with the processor clock >input. > 1.. My prototype uses a 16Mhz clock and works fine. My IAR CSpy was > limited to this frequency and I was successful with my development. I > now need to go to the full 48 Mhz speed the processor is capable of. > 2.. I have started using the PE Micro debugger which will work at 48Mhz > clock input. > 3.. My question is - should I use a 48 Mhz clock oscillator with the > resistor divider or stick to 16Mhz and use the PLL to step up to 48 Mhz? > 4.. My preference is to use the 48Mhz clock oscillator and not populate > the PLL filter. > 5.. Does anyone have any experience with this? >Thanks in advance for your help in this matter. >Regards, > >Steve Dillier > >HighPoint Technology LLC [Non-text portions of this message have been removed] |
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Re: Clock oscillator question - Oliver Betz - Mar 25 6:10:00 2004
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Doron Fael <> wrote: [...] > Then, after all the above discussion, I believe it would be easier for > you to use a lower frequency crystal or clock generator, and then use > the internal DP256 PLL to up the bus speed to the 24MHz you require. > The internal HCS12 PLL is pretty good, and most applications I am 100% agree. The problem is that people don't want to use the PLL initially because they don't understand it and are afraid to run into unknown problems. Motorola should emphasize the benefit of the PLL and make a clearer (simpler) statement on the selection of external components. The jitter warnings in the docs are contraproductive and IMHO unfounded. > aware of use it. In my opinion, you should consider not using the > internal PLL only if your application 1) Requires a fast start-up > after Reset with the final frequency (since the PLL takes time to > lock), or 2) Your application requires very high frequency stability > and low jitter, and cannot withstand the higher jitter and lower > frequency stability of a PLL circuit. Frequency stability is the same as the external clock or crystal, since it is "phase locked". Do you have any data about PLL jitter? At least with high reference clock, there can't be any jitter worth mentioning, i.e. only a small fraction of a bus cycle. But even "open loop" jitter of the VCO is small: using a D60A, in limp home mode I adjusted the voltage at XFC for ~8MHz E clock. The resulting jitter was less than 20ns ofer a 10us period. Oliver -- Oliver Betz, Muenchen |
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Re: Clock oscillator question - Steve-HighPoint - Mar 25 6:57:00 2004
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Doron: As always your input is excellent. I am going to take your advice and stick with 16 Mhz and use the PLL. I am also having second thoughts on the clock oscillator. My prototypes have worked fine with 16 Mhz and the resistor divider, but I have noticed a few spurious resets which I have not had time to track down. I think I should use a crystal based on your advice. Bottom line - I am going to use a crystal on rev B at 16Mhz and use the PLL to get to 48Mhz clock. Thanks again for your help. Steve Dillier HighPoint Technology ----- Original Message ----- From: Doron Fael To: Sent: Thursday, March 25, 2004 3:23 AM Subject: Re: [68HC12] Clock oscillator question Steve, The DP256 data sheets specify that when supplying 50MHz clock-generator signal with 2.5V voltage swing to the EXTAL pin, the rise time and fall time need to be no more than 0.5nSEC (the clock high and clock low time are required to be at least 9.5nSEC). My experience is that at room temperature this works, even with 1nSEC rise and fall time, but you might not want to risk it if your design needs to be tested at the temperature extremes and work even with both slow and normal silicon. With a voltage divider made of two 10K resistors (like used by your lower speed application), you need to also take into account a 5 - 10 pF capacitance on the EXTAL input. The effect of the capacitance and the two 10K resistors is long rise and fall times on the EXTAL input - on the order of no less than 5Kohm * 5pF = 25 nSEC - this is very far from the specified maximum of 0.5nSEC in the DP256 data sheets! Even if you reduce the resistors to 470ohm (which will increase the current consumption from your clock generator significantly), you will still have a time constant of no less than 1.25nSEC. Still marginal in my opinion - but might be operable - I am not sure. Another possibility, if you insist on using a clock generator, and supply 48MHz, is to use a Pericom 74ST1G125 buffer, powered by 2.5V, to buffer between your 5V clock generator, and the DP256 EXTAL input. This solution too has a draw-back: In Stop power-down mode the VDD and VDDPLL voltages generated internally in the DP256 may drop significantly to about 1.6V. If in this case, you continue to feed a 2.5V Clock to the EXTAL input, you may damage the DP256 device. The solution to this draw-back is either not use the STOP power-down mode, or connect Schottky (low voltage) diodes between your external 2.5V supply and the VDD and VDDPLL pins, so the external diodes pull the VDD and VDDPLL high when the internal voltage regulator drops the voltage. (this solution was offered to me by the Motorola HCS12 design team - so I am pretty sure it is safe to use). Then, after all the above discussion, I believe it would be easier for you to use a lower frequency crystal or clock generator, and then use the internal DP256 PLL to up the bus speed to the 24MHz you require. The internal HCS12 PLL is pretty good, and most applications I am aware of use it. In my opinion, you should consider not using the internal PLL only if your application 1) Requires a fast start-up after Reset with the final frequency (since the PLL takes time to lock), or 2) Your application requires very high frequency stability and low jitter, and cannot withstand the higher jitter and lower frequency stability of a PLL circuit. Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 13:38 24/03/2004 -0600, you wrote: >I am working on a project using either the 9s12A256 or the DP256 part. I >have on my board a clock oscillator running at 5VDC and using two 10K >resistors to divide the voltage to be compatible with the processor clock >input. > 1.. My prototype uses a 16Mhz clock and works fine. My IAR CSpy was > limited to this frequency and I was successful with my development. I > now need to go to the full 48 Mhz speed the processor is capable of. > 2.. I have started using the PE Micro debugger which will work at 48Mhz > clock input. > 3.. My question is - should I use a 48 Mhz clock oscillator with the > resistor divider or stick to 16Mhz and use the PLL to step up to 48 Mhz? > 4.. My preference is to use the 48Mhz clock oscillator and not populate > the PLL filter. > 5.. Does anyone have any experience with this? >Thanks in advance for your help in this matter. >Regards, > >Steve Dillier > >HighPoint Technology LLC [Non-text portions of this message have been removed] --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu o learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu ------------------------------------------------------------------------------ Yahoo! Groups Links a.. To [Non-text portions of this message have been removed] |
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Re: Clock oscillator question - Doron Fael - Mar 25 7:48:00 2004
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At 12:10 25/03/2004 +0100, "Oliver Betz" <> wrote: >Frequency stability is the same as the external clock or crystal, >since it is "phase locked". > >Do you have any data about PLL jitter? > >At least with high reference clock, there can't be any jitter worth >mentioning, i.e. only a small fraction of a bus cycle. In the context of instruction execution of the HCS12 micro, the jitter of the PLL is indeed negligible (assuming appropriate components are used in the PLL loop filter on the XFC pin). The PLL jitter might not be negligible, if the timer output, of the ECLK output is used for some very precise timing circuitry. For example, there are some applications (like Gigabit Ethernet and high-speed communication protocols) that require very low jitter - in the order of 1pSEC RMS from 12KHz - 20MHz. For such applications apparently practical PLLs cannot supply the required low jitter, and only special crystal based or saw based oscillators can supply the needed low jitter. Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html [Non-text portions of this message have been removed] |
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Re: Clock oscillator question - Oliver Betz - Mar 25 12:01:00 2004
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Doron Fael <> wrote: >>Do you have any data about PLL jitter? [...] >The PLL jitter might not be negligible, if the timer output, of the ECLK >output is used for some very precise timing circuitry. that must be a very special application needing much less than 1% tolerance even at very short durations. >For example, there are some applications (like Gigabit Ethernet and >high-speed communication protocols) that require very low jitter - in the ...but these won't be driven from the HC(S)12 bus clock. Ceterum censeo, Motorola should specify jitter, and remove unfounded jitter warnings from the docs. For example regarding CAN and PLL. Oliver -- Oliver Betz, Muenchen |
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