Stuck in "Self Clock Mode" | 68HC12

Code ran fine on 68hc9sC32 eval board. In fact the PLL init code I'm using was lifted from the eval kit. After changing register include file, REFDV and SYNR I loaded the code into my actual board which uses hc9s12A64 (die 2L86D). I am using a 7.3728MHz crystal and set my bus clock for 23.5MHz (REFDV = 4, SYNR = 15). I have also tried various REFDV and SYNR combinations. Observations: 1. CRGFLG reads back $43 immediately out of reset. The SCM flag is set, which I assume is why I can't clear CME (#2 below). WHY IS SCM SET?? If I understand SCM, the processor will revert to normal mode when the clock is reliable, yet it never does. 2. Crystal reliably begins oscillating ~850us after power up. Reset comes up about 850ms after OSC starts up. I tried to be as unobtrusive as possible (loading) in my clock measurement so I'm pretty confident in it. 3. I write 50 to PLLCTL to disable clock monitor, enable PLL and set ACQ to high BW . Immediately after write, PLLCTL reads back $D1. If I write $00 to PLLCTL it reads back $81. 4. The XFC pin is railed at 2.5V and it seems to make no attempt to hunt for a lock. Storage scope shows it jumping straight to 2.5V after power up. I assume this is due to the processor being in "Self Clock Mode"? 5. Tried a different frequency crystal (3.68MHz) � same problem. Thanks for any suggestions or insights! Regards, Sean Harnett

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Stuck in "Self Clock Mode" - cleancontrollers - Apr 4 9:09:00 2004