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Discussion Groups | 68HC12 | External memory
Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).
External memory - Andrew Lohmann's New Email Server - Apr 30 5:09:00 2004
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Hi,
Apologies for keep on bring this up on the group but, having built a new improved target,
I still can't access external ram reliably. My target is MC9S12E128. With the debugger connected I can write a small block of data fine. I can also write a MSB ok (A0=0), but when I attempt to write a LSB (!LSTRB = 0) then reading it back it fails. !LSTRB is connected to RAM's !UB, therefore there is no decoding logic in the !LSTRB. In order to avoid possible marginal timing !WE and !OE are generated from R/W and ECLK using a 74AC138. It is as if !LSTRB only operates when it is preceded by a MSB? Andrew Lohmann AIIE Design Engineer PLEASE NOTE NEW EMAIL ADDRESS IS: Bellingham + Stanley Ltd. Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England. Tel: +44 (0) 1892 500400 Fax: +44 (0) 1892 543115 Website: www.bs-ltd.com [Non-text portions of this message have been removed] |
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Re: External memory - zeta_alpha2002 - Apr 30 7:38:00 2004
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>!LSTRB is connected to RAM's !UB, It should be the otherway around, !LSTRB to !LB and A0 to !UB Cut and jumper tracks to fix. |
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Re: Re: External memory - Andrew Lohmann's New Email Server - Apr 30 8:08:00 2004
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Thanks Zeta_alpha,
That's how I had it before I cut tracks etc - there must be another fault e.g. !LSTRB pin
stuck low?
Andrew ----- Original Message ----- From: zeta_alpha2002 To: Sent: Friday, April 30, 2004 1:38 PM Subject: [68HC12] Re: External memory >!LSTRB is connected to RAM's !UB, It should be the otherway around, !LSTRB to !LB and A0 to !UB Cut and jumper tracks to fix. --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu o learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu ------------------------------------------------------------------------------ Yahoo! Groups Links a.. To [Non-text portions of this message have been removed] |
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Re: External memory - zeta_alpha2002 - Apr 30 9:39:00 2004
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The symptoms tells me as if memory access is out of sync with A0 or LSTRB. What memory devices are you using? Would you email the part number? Thanks.. --- In , "Andrew Lohmann's New Email Server" <andrew.lohmann@b...> wrote: > Thanks Zeta_alpha, > That's how I had it before I cut tracks etc - there must be another fault e.g. !LSTRB pin stuck low? > Andrew > ----- Original Message ----- > From: zeta_alpha2002 > To: > Sent: Friday, April 30, 2004 1:38 PM > Subject: [68HC12] Re: External memory > >!LSTRB is connected to RAM's !UB, > > It should be the otherway around, !LSTRB to !LB and A0 to !UB > Cut and jumper tracks to fix. > > > --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > o learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > > > -------------------------------------------------------------------- ---------- > Yahoo! Groups Links > > a.. To > > [Non-text portions of this message have been removed] |
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Re: Re: External memory - Andrew Lohmann's New Email Server - Apr 30 10:04:00 2004
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Hi Zeta Alpha,
It is IDT71V016SA15PH, but I have confirmed that !LSTRB is low, but not shorted to 0V.
Incidentally the swap you suggested, which is how I have now, is contrary to application
note AN2408 - but then you can't believe everything can you. In that app note !LSTRB
drives !UB?
Thanks Andrew ----- Original Message ----- From: zeta_alpha2002 To: Sent: Friday, April 30, 2004 3:39 PM Subject: [68HC12] Re: External memory The symptoms tells me as if memory access is out of sync with A0 or LSTRB. What memory devices are you using? Would you email the part number? Thanks.. --- In , "Andrew Lohmann's New Email Server" <andrew.lohmann@b...> wrote: > Thanks Zeta_alpha, > That's how I had it before I cut tracks etc - there must be another fault e.g. !LSTRB pin stuck low? > Andrew > ----- Original Message ----- > From: zeta_alpha2002 > To: > Sent: Friday, April 30, 2004 1:38 PM > Subject: [68HC12] Re: External memory > >!LSTRB is connected to RAM's !UB, > > It should be the otherway around, !LSTRB to !LB and A0 to !UB > Cut and jumper tracks to fix. > > > --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > o learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > > > -------------------------------------------------------------------- ---------- > Yahoo! Groups Links > > a.. To > > [Non-text portions of this message have been removed] --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu o learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu ------------------------------------------------------------------------------ Yahoo! Groups Links a.. To [Non-text portions of this message have been removed] |
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Re: Re: External memory - Stephen Trier - Apr 30 12:26:00 2004
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Andrew, The 812A4 board I'm working on has /LSTRB wired to /UB and A0 wired to /LB on the RAM. My colleagues and I got it backwards the first time, too. Stephen -- Stephen Trier Technical Development Lab Cleveland FES Center |
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Re: Re: External memory - Andrew Lohmann's New Email Server - May 4 4:43:00 2004
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Thanks - I have a fault of some kind where the !LSTRB is low, but not stuck low. I've just had another look at my software:- ; Move internal ram movb #(RAM14 | RAM13 | RAM12 | RAM11 | RAMHAL), INITRM ; Internal Ram from $7fff down. lds #__stack ; initialise stack pointer (Cosmic) //1 ; Expansion Bus settings based on: AN2408/D, but in the order of Axiom example ; & no PIPOE indicate the instruction queue //2 movb #(LSTRE | RDWE), PEAR // original value AL 04-05-04 //3 movb #ESTR, EBICTL // Original Value //4 // movb #MODC | MODB | MODA | EMK | EME, MODE ; Normal Expanded Wide, No visibility of internal ops movb #MODC | MODB | MODA, MODE ; Normal Expanded Wide, No visibility of internal ops //5 movb #ROMHM | ROMON, MISC ;min 0 no stretching, $0000-$7FFF external, target good. AL 26-02-04 At reset !LSTRB is high, it goes low at line 5. line 4 has an alternative which make no difference if compiled with the alliterative. I guess I could patch it up by adding an inverter between decoded address 0 and !UB, but I don't want to do that just yet. Andrew ----- Original Message ----- From: Stephen Trier To: Sent: Friday, April 30, 2004 6:26 PM Subject: Re: [68HC12] Re: External memory Andrew, The 812A4 board I'm working on has /LSTRB wired to /UB and A0 wired to /LB on the RAM. My colleagues and I got it backwards the first time, too. Stephen -- Stephen Trier Technical Development Lab Cleveland FES Center --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu o learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu ------------------------------------------------------------------------------ Yahoo! Groups Links a.. To [Non-text portions of this message have been removed] |
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Re: External memory - zeta_alpha2002 - May 4 5:11:00 2004
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> Thanks - I have a fault of some kind where the !LSTRB is low, but >not stuck low. What are you settings for the expansion registers? Below are my settings. I have mapped RAM at PPAGE = $10 to $17. Where is your RAM mapped to? goCheckRAM movb #$0C,PEAR ;$0C ->Enable LSTRE,RDWE = 1 movb #$E3,MODE ;$E3 -> Enable MODC,MODA,MODB,EMK,EME = 1 movb #$01,EBICTL ;$01 -> Enable ESTR = 1 movb #$0D,MISC ;$0F ->Enable EXSTR1, EXSTR0,ROMHM,ROMON = 1 |
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Re: Re: External memory - Andrew Lohmann's New Email Server - May 4 6:33:00 2004
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I've got it running. Slowing the memory, which should not be necessary, got it to
work. Cosmic Zap unfortunately misled me, if I change the a nibble in the memory browse
window then scroll it to update memory it reverts to its previous value - if I change a
byte (two nibbles) or more it works fine. The answer to the question is - I'm using near memory 0x2000 to 0x7fff, where internal ram is located from 0x7fff down to 0x6000, therefore I have a 16K block of external memory. The remaining 96K or memory used the first 7 pages of far memory - if I've worked it out properly? I don't need page ram for this application at this stage anyway. Thanks for all your help. Andrew Lohmann AIIE Design Engineer PLEASE NOTE NEW EMAIL ADDRESS IS: Bellingham + Stanley Ltd. Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England. Tel: +44 (0) 1892 500400 Fax: +44 (0) 1892 543115 Website: www.bs-ltd.com ----- Original Message ----- From: zeta_alpha2002 To: Sent: Tuesday, May 04, 2004 11:11 AM Subject: [68HC12] Re: External memory > Thanks - I have a fault of some kind where the !LSTRB is low, but >not stuck low. What are you settings for the expansion registers? Below are my settings. I have mapped RAM at PPAGE = $10 to $17. Where is your RAM mapped to? goCheckRAM movb #$0C,PEAR ;$0C ->Enable LSTRE,RDWE = 1 movb #$E3,MODE ;$E3 -> Enable MODC,MODA,MODB,EMK,EME = 1 movb #$01,EBICTL ;$01 -> Enable ESTR = 1 movb #$0D,MISC ;$0F ->Enable EXSTR1, EXSTR0,ROMHM,ROMON = 1 --------------------------------------------------------To learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu o learn more about Motorola Microcontrollers, please visit http://www.motorola.com/mcu ------------------------------------------------------------------------------ Yahoo! Groups Links a.. To [Non-text portions of this message have been removed] |
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Re: Re: External memory - Andrew Lohmann's New Email Server - May 5 5:13:00 2004
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A follow up question. My target E128 is running fine with 16K of external RAM, 0 stretches at 16MHz. Does anyone know what the XA pins do when accessing near memory (below 0x8000)? They need to XA14 = A14, XA15 = A15, and XA16..18 = 0. I don't know if this is the case and have added extra logic gates just in case - therefore can I remove redundant AND gates? Andrew Lohmann AIIE Design Engineer PLEASE NOTE NEW EMAIL ADDRESS IS: Bellingham + Stanley Ltd. Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England. Tel: +44 (0) 1892 500400 Fax: +44 (0) 1892 543115 Website: www.bs-ltd.com [Non-text portions of this message have been removed] |
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