Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).
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Problems here with my first 9S12 board, was wondering if this sounds familiar to anybody... I have a new MC9S12DJ64CPV design that I'm driving with an 8mHz, 5 volt oscillator. The oscillator output reaches the EXTAL pin after being divided down to 2.5 volts through 2, 470 ohm resistors. There is some rounding, but the clock looks pretty good. The circuit is very basic and otherwise exactly like an Elektronikladen "CardS12" with most of the lines not terminated, but connected to 1 or 2 inches of traces on a not-yet-populated board. MODA, MODB, are tied low through 10k's. XTAL is open. XIRQ tied hi through 100k. XCLKS is now tied lo through a small resistor, I have also tried it tied hi. The Motorola docs make contradictory recommendations for XCLKS when using an external oscillator. I have also tried tried shorting together VDDPLL and XFC, as recommended by Motorola for non-pll operation, no difference. Basically, *most of the time* I can't get a ComPod12-Pro to recognize the chip. When I plug in the ComPod12-Pro, I notice that I get a ~1.48mHz ECLK...is this normal? But a very small percentage of the time, the BDM does work! Have tried all the varations of plugging-in/powering up/restarting the program/ComPod target settings and frequencies. The ComPod works fine with several older HC912 boards. I've swapped out the CPU a few times (just now discovered how to use the heat-gun for that, it so easy...). All the power connections are correct. Would appreciate any input! WAG's are always welcome here. Bill T. |
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On Sun, May 09, 2004 at 11:06:41PM -0000, tonalbuilder2002 wrote: > > Basically, *most of the time* I can't get a ComPod12-Pro to > recognize the chip. When I plug in the ComPod12-Pro, I notice that I > get a ~1.48mHz ECLK...is this normal? But a very small percentage of > the time, the BDM does work! Have tried all the varations of I have exactly the same configuration with my DP256 : only the clock divider exists of 2 * 10 K resistor directly driven with a ACT74 @ 4 MHz. I tied XCLKS high with a 10 K pullup. The 2.5 V clock to the DP256 looked like a sawtooth but my DP256 works flawlessy. I experienced the same problems with the bdm : I discovered that my reset signal came up to slow (I used a TL7705 for this). My solution was to delay my bdm signal to the BKGND pin for a (very) short time only during reset, so that the bdm sigal was low when reset was going high and being stable. My DP256 always entered into bdm afterwards. Armand ******************************************* * choose GNU/Linux : GNU/Linux is Freedom * ******************************************* ---------------------------------- Armand ten Doesschate Welschapsedijk 141 5652 XL Eindhoven the Netherlands tel : (++31) 40 2571 274 e-mail : a_DOT_doesschate_AT_hccnet_DOT_nl |
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Bill, PE7/XCLKS needs to be connected to a 2.2Kohm or lower resistance pull-down resistor to GND, to select the external clock oscillator. The low resistance is needed in order to overcome an internal pull-up resistor that is present on PE7/XCLKS during and after Reset. The 1.48MHz ECLK that you measure suggests that your 9S12DJ64 is in Limp-Home - Self-Clock mode, and is generating its own low frequency internally, because it can't detect a valid frequency externally for some reason (likely because of improper XCLKS settings). When the 9S12DJ64 will detect the correct 8MHz frequency that you try driving into EXTAL, it will show a 4MHz clock on ECLK (half EXTAL rate out of Reset, and as long as the internal PLL is not selected). Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 23:06 09/05/2004 +0000, you wrote: >Problems here with my first 9S12 board, was wondering if this sounds >familiar to anybody... > >I have a new MC9S12DJ64CPV design that I'm driving with an 8mHz, 5 >volt oscillator. The oscillator output reaches the EXTAL pin after >being divided down to 2.5 volts through 2, 470 ohm resistors. There >is some rounding, but the clock looks pretty good. The circuit is >very basic and otherwise exactly like an Elektronikladen "CardS12" >with most of the lines not terminated, but connected to 1 or 2 inches >of traces on a not-yet-populated board. > >MODA, MODB, are tied low through 10k's. > >XTAL is open. > >XIRQ tied hi through 100k. > >XCLKS is now tied lo through a small resistor, I have also tried it >tied hi. The Motorola docs make contradictory recommendations for >XCLKS when using an external oscillator. > >I have also tried tried shorting together VDDPLL and XFC, as >recommended by Motorola for non-pll operation, no difference. > >Basically, *most of the time* I can't get a ComPod12-Pro to >recognize the chip. When I plug in the ComPod12-Pro, I notice that I >get a ~1.48mHz ECLK...is this normal? But a very small percentage of >the time, the BDM does work! Have tried all the varations of >plugging-in/powering up/restarting the program/ComPod target >settings and frequencies. The ComPod works fine with several older >HC912 boards. I've swapped out the CPU a few times (just now >discovered how to use the heat-gun for that, it so easy...). All the >power connections are correct. > >Would appreciate any input! WAG's are always welcome here. > >Bill T. [Non-text portions of this message have been removed] |
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Armand, Please take the following as a constructive criticism. I don't mean to insult anybody. I wouldn't recommend the design as you suggest here: When XCLKS is tied high through a pull-up, the DP256 is expecting to receive a Colpitts Crystal, which is not what you have. I would also be concerned of using two 10K resistors for the clock Oscillator voltage divider. The time constant you get is 5Kohm of equivalent resistance (the two 10K resistors in parallel), and approximately 10pF of input capacitance on EXTAL, which yields a 50nSEC time constant. You are using a 4MHz clock that has a high and a low time of about 125nSEC. Taking into account that the charge up to a valid logic level takes 3 - 5 time constants, the EXTAL clock input will not get to valid clock levels. I think you may have design that is working, but not as intended and specified in the data sheets. As a designer of BDMs and emulators, I also don't approve of making any tricks on the BKGD line like delaying it. BDMs function best when the BKGD and the Reset lines are connected directly from the BDM POD to the HCS12 pins, with nothing to interfere between them. I don't know if you have the specified configuration working on one test board or many production boards, but if I were instead of you, I would look into fixing these points, so the design works as intended by the silicon maker. Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 07:35 10/05/2004 +0200, you wrote: >I have exactly the same configuration with my DP256 : only the clock >divider exists of 2 * 10 K resistor directly driven with a ACT74 @ 4 MHz. >I tied XCLKS high with a 10 K pullup. The 2.5 V clock to the DP256 looked >like a sawtooth but my DP256 works flawlessy. > >I experienced the same problems with the bdm : I discovered that my >reset signal came up to slow (I used a TL7705 for this). My solution was >to delay my bdm signal to the BKGND pin for a (very) short time only during >reset, so that the bdm sigal was low when reset was going high and being >stable. My DP256 always entered into bdm afterwards. >Armand >******************************************* >* choose GNU/Linux : GNU/Linux is Freedom * >******************************************* > >---------------------------------- > >Armand ten Doesschate >Welschapsedijk 141 >5652 XL Eindhoven >the Netherlands >tel : (++31) 40 2571 274 >e-mail : a_DOT_doesschate_AT_hccnet_DOT_nl [Non-text portions of this message have been removed] |
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On Mon, May 10, 2004 at 10:35:58AM +0300, Doron Fael wrote: > Armand, > > Please take the following as a constructive criticism. I don't mean to > insult anybody. > > I wouldn't recommend the design as you suggest here: > > When XCLKS is tied high through a pull-up, the DP256 is expecting to > receive a Colpitts Crystal, which is not what you have. > > I would also be concerned of using two 10K resistors for the clock > Oscillator voltage divider. The time constant you get is 5Kohm of > equivalent resistance (the two 10K resistors in parallel), and > approximately 10pF of input capacitance on EXTAL, which yields a 50nSEC > time constant. You are using a 4MHz clock that has a high and a low time of > about 125nSEC. Taking into account that the charge up to a valid logic > level takes 3 - 5 time constants, the EXTAL clock input will not get to > valid clock levels. I think you may have design that is working, but not as > intended and specified in the data sheets. This was just an experiment : I implemented a collpits configuration before. Anyway I certainly agree that it shouldnot go into production. I also fixed the reset circuit ... > Hope this helps, > Doron > Nohau Corporation > HC12 In-Circuit Emulators > www.nohau.com/emul12pc.html Armand ******************************************* * choose GNU/Linux : GNU/Linux is Freedom * ******************************************* ---------------------------------- Armand ten Doesschate Welschapsedijk 141 5652 XL Eindhoven the Netherlands tel : (++31) 40 2571 274 e-mail : a_DOT_doesschate_AT_hccnet_DOT_nl |
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> XCLKS is now tied lo through a small resistor, I have also tried it > tied hi. The Motorola docs make contradictory recommendations for > XCLKS when using an external oscillator. Hi Bill, low is fine in your case. Please note that the CRG module data sheet is talking about the (internal) signal XCLKS while the device guide is describing the (external) pin /XCLKS. That's the source of the negation - and a lot of confusion as well :-) good luck! Oliver |
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Thanks to all of you who helped with this problem. There are some real experts on this group! Well, duh! Bringing up a new, expensive board layout is always a very stressful time and at least I hate to even think that something might not be right. I hurried up too much in design and tied VDD1 and VDD2 to VCC...the poor 9S12 did not like having its insides exposed to 5 volts! If I had just checked another 1 or 2 hours before layout... But at least I learned about the "limp home" clock and few other things. Now everything is fine, and I must say that the ComPod12-Pro is very, very FAST and a delight to use. Many Thanks to All, Bill T. |