912D60A *min* Frequency of operation? | 68HC12

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My basic question is this: is the D60A a "fully static" design? I'm looking at a new design using the 912D60A, and I've noticed an unusual spec change from the (older) 912B32 that I'm more familiar with: * The 'B32 spec's a minimum freq. for f0 (ECLK) as DC (see table 19.14 in M68HC12B/D-Rev 8.0). * The 'D60A has a non-zero minimum frequency spec of 4 kHz (see table 20-12 in MC68HC912D60A/D-Rev 3). I understand there is a minimum operating freq. associated with the PLL, but I am using an external clock with VDDPLL grounded. Similarly, other subsystems (like the ADC, or writing to byte-EEPROM) will have minimum freq. requirements, but aside from that I understood the HC12's to be completely static designs, like the older HC11. A (related?) myster spec in table 20-10 is the min F_READ > 32kHz for the Flash EE read bus clock frequency. Does this mean that for s-l-o-w ECLK's, the flashEE is somehow unreadable? This seems very different from the 'B32, and I want to make sure I have a clear understanding of what's going on under the hood. Thanks for any clarifications you might have. --Matt

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Discussion Groups | 68HC12 | 912D60A min Frequency of operation?

912D60A min Frequency of operation? - mkowitt - May 12 11:29:00 2004