Why I can't use the PLL in MC9S12DP256B in Normal Single-Chip Mode | 68HC12

68HC12，您好！ I have programmed a simlpe demonstration program to see the MC9S12DP256B to run in Normal Single-Chip Mode.The program is to generates 60 1-second,active-low pulses on PB0. At first I use the default settings out of reset,while I use a 16MHz puartz,the default bus clock is 8 MHz.Load the programmer to the target MCU,runn,a 60 1-second,active-low pulses is generated on PB0. Second,I swtich the PLL on leaving the SYNR and REFDV register zero.The bizarrerie thing happened.While debug the programmer in single step modle untill switch the System clocks to PLLCLK(set PLLSEL bit in CLKSEL),and then run the pramgrammer a a 60 0.5-second,active-low pulses is generated on PB0.But when I run the pragrammer from the beginning or reset the MCU from the target board the System clocks can't switch to PLL,and a 60 1-second,active-low pulses is generated. And the PLLSEL bit in CLKSEL is not set. 　　　　　　　　致礼！　　　　　　　　曹树华　　　　　　　　　　　　　　　　　　2004-04-22

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There is a problem that the LOCK bit sometimes reports that the PLL is locked and can be selected, where in fact it is not yet locked. (in other words the lock bit is lying). My colleague Steve Russell came up with an algorithm to overcome this problem with the lock bit. Here is a quote of his algorithm: ****************************** At the heart of a PLL is a "phase detector" that compares the reference frequency divided by the reference divider with the oscillator frequency divided by the other divider. One of the PLL design challenges is correctly indicating when the PLL is locked through all the states of the phase detector. I have seen some otherwise satisfactory designs that did not meet this challenge. To avoid most of the problems that show up in lock indication logic, what we do is: 1. Calculate the period of the phase detector. ( Ext clock / Reference divisor ) Usually this can be calculated at compile or assemble time 2. Turn on the PLL, but don't select it. 3. If the time since the PLL was turned is too long (1 second or 1000 phase detector periods, your choice), declare a failure to lock and give up. 4. Wait for the lock bit to be one. 5. Keep testing the lock bit for 1 for 10 to 100 periods of the phase detector. 6. If the lock bit goes to 0 during this wait, go back to step 3. 7. Switch the system clock to the PLL A wait of 10 periods of the phase detector is conservative. A wait of 100 periods is very conservative. I'd like to emphasize that when a PLL is not locked, it often varies its frequency very rapidly, and most processor designs just plain stop operating correctly when they get this sort of erratic clock. If you switch system clock to an unlocked PLL you often get a system that fails to execute instructions correctly. ****************************** You may also have improper values for the PLL loop filter on the Xfc pin. You can use the following calculator to calculate proper values for C0, R0, and Ca, that may work better: http://www.nohau.com/s12calc/pll_302.html Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 10:51 22/04/2004 +0800, you wrote: >68HC12，您好！ > I have programmed a simlpe demonstration program to see the > MC9S12DP256B to run in Normal Single-Chip Mode.The program >is to generates 60 1-second,active-low pulses on PB0. > At first I use the default settings out of reset,while I use a 16MHz > puartz,the default bus clock is 8 MHz.Load the programmer to the target > MCU,runn,a 60 1-second,active-low pulses is generated on PB0. > Second,I swtich the PLL on leaving the SYNR and REFDV register > zero.The bizarrerie thing happened.While debug the programmer in single > step modle untill switch the System clocks to PLLCLK(set PLLSEL bit in > CLKSEL),and then run the pramgrammer a a 60 0.5-second,active-low pulses > is generated on PB0.But when I run the pragrammer from the beginning or > reset the MCU from the target board the System clocks can't switch to > PLL,and a 60 1-second,active-low pulses is generated. And the PLLSEL bit > in CLKSEL is not set. > >　　　　　　　　致 >礼！ >　　　　　　　　曹树华 >　　　　　　　　 >　　　　　　　　　　2004-04-22 [Non-text portions of this message have been removed]

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Discussion Groups | 68HC12 | Why I can't use the PLL in MC9S12DP256B in Normal Single-Chip Mode

Why I can't use the PLL in MC9S12DP256B in Normal Single-Chip Mode - 曹树华 - Apr 21 21:51:00 2004

Re: Why I can't use the PLL in MC9S12DP256B in Normal Single-Chip Mode - Doron Fael - Jul 22 2:07:00 2004