Memory retention on DP256 | 68HC12

Hi, I am new to the DP256. I need to reserve a data structure during power failures. I have two questions: 1) Is the DP256 internal static ram in a random state after power up 2) How or to what pin can I connect a 3.3V battery to reserve the state of the internal memory. The ideal condition would be to have only the sram access to a retention power source and prohibit any other pheriperal on the DP256 to be alive and draw/drain the battery - is this possible? The method in mind would be to store each data session with a CRC. This way I can confirm whether the content did get corrupted during a power surge. Thanks very much Fred Glaum [Non-text portions of this message have been removed]

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Hello Fred, The MC9S12DP256 does not have a specific pin to retain the content of only the internal RAM. There are however two possibilities which may be close enough for you to use. 1. The DP256 has a 4KByte internal EEPROM that is intended to store non-volatile data. Each EEPROM sector (4 bytes) is specified to be erased and written up to 10,000 times. This means that you cannot write to it too often, as otherwise you will exceed the maximum number of allowed erase and write cycles too early. You also need special routines to write new data to the EEPROM, and these writes are pretty slow, and require some timed delays. Reads from the EEPROM are done at full-speed and you can read as many times as you like without affecting the EEPROM. 2. If the use of the EEPROM is not an option, and you must have the content retained in the internal RAM, the closest thing would be the "STOP Power-Down mode". The STOP power-down state is initiated by the STOP instruction, after initializing the appropriate flag in the CCR register to allow the STOP power-down. In STOP power-down all the clocks to the CPU are halted, and you can determine on a per peripheral basis which should be turned off or on during the STOP power-down. You need to supply 5V during the stop power-down to all the DP256 5V voltage pins (VDDX, VDDR, VDDA and VRH), but the current consumption is reduced (typically 25uA at room temperature), to only sustain the content of the internal RAM, SFR Registers, and CPU registers. The wake-up from the STOP power-down is done either using any interrupt that was enabled before the power-down mode, or using Reset. Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 23:20 21/11/2004 -0800, you wrote: >Hi, > >I am new to the DP256. I need to reserve a data structure during power >failures. I have two questions: > >1) Is the DP256 internal static ram in a random state after power up >2) How or to what pin can I connect a 3.3V battery to reserve the state of >the internal memory. > >The ideal condition would be to have only the sram access to a retention >power source and prohibit any other pheriperal on the DP256 to be alive >and draw/drain the battery - is this possible? > >The method in mind would be to store each data session with a CRC. This >way I can confirm whether the content did get corrupted during a power surge. > >Thanks very much > >Fred Glaum [Non-text portions of this message have been removed]

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Discussion Groups | 68HC12 | Memory retention on DP256

Memory retention on DP256 - fed - Nov 22 2:20:00 2004

Re: Memory retention on DP256 - Doron Fael - Nov 22 3:12:00 2004