IIC bus locks | 68HC12 | EmbeddedRelated.com

Flavio, I never fixed the problem but situation seems not to arise under normal use and proper circuit board. Problem was really detected when prototyping with some wiring attached on board. Anyway I'm still interested in a good fix to prevent it. My intention was to force the state and try some bit banging as yours to release the bus, but other tasks kept me away from this matter. Please keep us informed of any progress. Jordi Costa ----- Original Message ----- From: "Flavio Protasio Ribeiro" <> To: <> Sent: Monday, February 07, 2005 5:52 PM Subject: [68HC12] IIC bus locks > > > Hello, > > On October 2004 Jordi Costa posted the following: > > "I have HCS12 communicating with just an IIC slave device (M41T56, > DS1307). If for some reason (program restart, parasitic noise on bus, > .......) communication is stopped while slave is sending a 0, SDA line > is held down and the master cannot control the bus again and an > arbitration error is returned." > > I don't know if he managed to find a solution, and I've got the same > problem with an HCS12. The IIC spec says that the procedure to > software reset the bus is the following: > > 1. send 9 clock pulses on SCL with SDA high > 2. send a STOP > > The idea is that sometime during the 9 pulses the slave-transmitter > will release SDA and expect an ACK. It will get a NACK from the master > (the HCS12), since we let SDA=1. The slave will then release the bus. > > This works fine if I disable the IIC module and bit bang on > PORTJ[6:7], but I was also looking for a better solution involving the > IIC module. > > The MCF5307 Coldfire also has an IIC module, and it is essentially > identical the the HCS12's. Its manual states the following on page > 8-10: > > "If IBSR[IBB] when the I2C bus module is enabled, execute the > following code sequence before proceeding with normal initialization > code. This issues a STOP command to the slave device, placing it in > idle state as if it were just power-cycled on." > > I2CR = 0x0 > I2CR = 0xA > dummy read of I2DR > IBSR = 0x0 > I2CR = 0x0 > > Unfortunately this is rubbish. The commands don't even make any sense, > since I2CR = 0xA writes to a reserved bit. > > Does anyknow know how to software reset the IIC bus using the IIC > module? I'm trying to get an answer out of Freescale's support, but > the person answering my service requests doesn't seem to understand > what I really want. > > Thanks for your attention. > > Best regards, > > Flavio

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Re: IIC bus locks - Jordi Costa - Feb 7 13:22:00 2005