Sign in
Search AT91SAM
Subscribe to AT91SAM
Ads
Discussion Groups
Discussion Groups | AT91SAM ARM | AT91SAM7SE512 ADC behavior
For users of the Atmel AT91SAM7 and AT91SAM9 ARM CPU chips. Atmel has taken a new direction by combining on chip flash and ram with the ARM CPU on a single die. This provides low cost devices for small systems using the ARM CPU. This group is to exchange information to help users get started and learn how to use the devices.
AT91SAM7SE512 ADC behavior - birdiezong - Feb 25 14:10:16 2008
hello everyone,
I'm working on the AT91SAM7SE512 ADC, and my goal is to setup the ADC
to use a Timer Counter channel as the trigger and read the conversion
results in an ISR.
As an intermediate step, I setup the ADC to software trigger only with
interrupt enabled. This way, I can manually trigger a conversion and
watch the interrupt working properly. However I'm seeing some strange
behaviors and the interrupt doesn't work properly.
The ADC is setup to have a clock 4.8MHz, minimal startup and sample
and hold time, software trigger only, normal mode, 10-bit resolution,
channel 0 and 1. The interrupt is setup to be edge triggered on EOC
bits 0 and 1.
The ISR is setup to toggle some LEDs (so that I know the ISR is being
executed), and read the channels 0 and 1 CDRs, before clearing the
interrupt.
It doesn't seem like the ISR is being executed, as no LEDs are
blinking and when I setup breakpoints to the ISR, the code doesn't
break. No conversion results are read either.
However, if I read the CDRs outside of the ISR, I'll get the correct
ADC readings, the SR is reset is 0xC0000, and the ISR can be triggered
correctly as a result of the SR reset.
So a couple of questions:
1) can the EOC bits be cleared in an ISR?
2) When the CDRs are read outside of the ISR, why is the SR reset to
0xC0000? I thought reading the appropriate CDRs only clear the
corresponding EOCs bits.
The datasheet and the errata didn't offer satisfactory answers, and
I'd appreciate any suggestions/inputs.
Lei
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
I'm working on the AT91SAM7SE512 ADC, and my goal is to setup the ADC
to use a Timer Counter channel as the trigger and read the conversion
results in an ISR.
As an intermediate step, I setup the ADC to software trigger only with
interrupt enabled. This way, I can manually trigger a conversion and
watch the interrupt working properly. However I'm seeing some strange
behaviors and the interrupt doesn't work properly.
The ADC is setup to have a clock 4.8MHz, minimal startup and sample
and hold time, software trigger only, normal mode, 10-bit resolution,
channel 0 and 1. The interrupt is setup to be edge triggered on EOC
bits 0 and 1.
The ISR is setup to toggle some LEDs (so that I know the ISR is being
executed), and read the channels 0 and 1 CDRs, before clearing the
interrupt.
It doesn't seem like the ISR is being executed, as no LEDs are
blinking and when I setup breakpoints to the ISR, the code doesn't
break. No conversion results are read either.
However, if I read the CDRs outside of the ISR, I'll get the correct
ADC readings, the SR is reset is 0xC0000, and the ISR can be triggered
correctly as a result of the SR reset.
So a couple of questions:
1) can the EOC bits be cleared in an ISR?
2) When the CDRs are read outside of the ISR, why is the SR reset to
0xC0000? I thought reading the appropriate CDRs only clear the
corresponding EOCs bits.
The datasheet and the errata didn't offer satisfactory answers, and
I'd appreciate any suggestions/inputs.
Lei
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )