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Discussion Groups | AT91SAM ARM | DMA Controller in AT91SAM9RL64
For users of the Atmel AT91SAM7 and AT91SAM9 ARM CPU chips. Atmel has taken a new direction by combining on chip flash and ram with the ARM CPU on a single die. This provides low cost devices for small systems using the ARM CPU. This group is to exchange information to help users get started and learn how to use the devices.
DMA Controller in AT91SAM9RL64 - "ICLI, Bekir (EXT)" - Feb 26 9:43:51 2008
Hi all,
I am trying to get familiar with DMAC in AT91SAM9RL64 and have seen something puzzling that I cannot find the reason.
When I give, as source and destination addresses, a memory location in internal SRAM, I cant see that copy has occurred.
(I am simply printing the contents of the destination and source, after copy)
However, if I give a location from SDRAM of devkit, I do see the result of the copy operation.
PS: I have configured the DMA according to the description given in the manual for "single buffer transfer".
PS2: I am not doing any MMU initialization, so the memories should be noncachable.
Can anybody explain this?
Mit freundlichem Gruß / Best regards
Bekir ICLI
Siemens AG
Automation and Drives, Automation and Drives, A&D SC IC RD4
Tel. : +49 (721) 595-3280
mailto:b...@siemens.com
http://www.siemens.com/automation
Siemens Aktiengesellschaft: Chairman of the Supervisory Board: Gerhard Cromme
Managing Board: Peter Loescher, Chairman, President and Chief Executive Officer;
Wolfgang Dehen, Heinrich Hiesinger, Joe Kaeser, Erich R. Reinhardt, Hermann Requardt,
Siegfried Russwurm, Peter Y. Solmssen
Registered offices: Berlin and Munich;
Commercial registries: Berlin Charlottenburg, HRB 12300, Munich, HRB 6684
WEEE-Reg.-No. DE 23691322
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
I am trying to get familiar with DMAC in AT91SAM9RL64 and have seen something puzzling that I cannot find the reason.
When I give, as source and destination addresses, a memory location in internal SRAM, I cant see that copy has occurred.
(I am simply printing the contents of the destination and source, after copy)
However, if I give a location from SDRAM of devkit, I do see the result of the copy operation.
PS: I have configured the DMA according to the description given in the manual for "single buffer transfer".
PS2: I am not doing any MMU initialization, so the memories should be noncachable.
Can anybody explain this?
Mit freundlichem Gruß / Best regards
Bekir ICLI
Siemens AG
Automation and Drives, Automation and Drives, A&D SC IC RD4
Tel. : +49 (721) 595-3280
mailto:b...@siemens.com
http://www.siemens.com/automation
Siemens Aktiengesellschaft: Chairman of the Supervisory Board: Gerhard Cromme
Managing Board: Peter Loescher, Chairman, President and Chief Executive Officer;
Wolfgang Dehen, Heinrich Hiesinger, Joe Kaeser, Erich R. Reinhardt, Hermann Requardt,
Siegfried Russwurm, Peter Y. Solmssen
Registered offices: Berlin and Munich;
Commercial registries: Berlin Charlottenburg, HRB 12300, Munich, HRB 6684
WEEE-Reg.-No. DE 23691322
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )