I'm designing a board with an AT92SAM9260 on it. I've run into three
questions that seem unanswerable from the Atmel datasheet alone:

Is the SHDN pin low or high when the device is in shutdown mode? This
is ambiguous and mentioned in several places. Page 5 says it's driven
at 0V only, so it's an open-collector output. Page 127 says software
can "assert" the SHDN pin, which, since it's an open-drain output,
implies SHDN is low when in shutdown mode. Page 128 seems to confirm
this by saying that shutdown is released or de-asserted on the wkup
input or an rtt event. The only conflicting information is that Atmel
has been very good about telling us when signals are active low by
putting an "N" as the first character of their names, like NRST
(active-low reset input). So if this pin really is low when in
shutdown mode, shouldn't it be either named NSHDN or just AWAKE?

Are the jtag lines run at the core voltage (1.8V) or at one of the
VDDIO voltages (3.3V)? From page 5 of the datasheet, it says that
JTAGSEL is a 1.8V signal, but it doesn't mention the others. There's
another list on page 64 and a description of the signals on page 65,
but voltage levels aren't mentioned. I'm using a QFP-208 and the
signals in question are located between two VDDIO pin (pins 24 & 32)
and a VDDCORE pin (pin 38), so it's still unclear. I'd assume they're
all 1.8V, but there's an olimex board (SAM9-L9260) that pulls them up
to 3.3V.

What's the leakage current into / out of the WKUP and SHDN pins? I
want to make sure I'm using as little current as possible while in
shutdown mode but still keep the signals pulled up/down to valid logic
levels (what those are is also unclear from the datasheet, page 749,
since it only lists valid low/high levels for the pins powered by the
VDDIOs).

I don't have a development board, or I would measure these things myself.

Help on any or all of the above questions would be appreciated!



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