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Discussion Groups | AT91SAM ARM | PWM master clock problem
For users of the Atmel AT91SAM7 and AT91SAM9 ARM CPU chips. Atmel has taken a new direction by combining on chip flash and ram with the ARM CPU on a single die. This provides low cost devices for small systems using the ARM CPU. This group is to exchange information to help users get started and learn how to use the devices.
PWM master clock problem - birdiezong - Apr 16 18:20:57 2008
Hello everyone,
I have a strange problem that I would like to get some help on.
My AT91SAM7SE512 processor runs off of a 18MHz crystal and internally
boosts up the master frequency to 48MHz.
When I setup PWM channels, here's what I did:
// enable PWM clock in PMC
pPMC->PMC_PCER = 1 << AT91C_ID_PWMC;
// Enable PWM Output on PIO pins
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA0_PWM0|AT91C_PA1_PWM1, 0);
// Stop the PWM
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0
|AT91C_PWMC_CHID1);
// Set the clock A divider to MCK
AT91C_BASE_PWMC->PWMC_MR = 1;
// Set the Clock
AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA|AT91C_PWMC_CPOL;
AT91C_BASE_PWMC_CH1->PWMC_CMR = MCKtoPWM | AT91C_PWMC_CPOL;
...
At this point I expect to see channel 0 and 1 both have MCK frequency
which should be 48MHz. However, when I probed them on a scope, I'm
getting ~187.5KHz, which is 48MHz/256.
I tried several variants on the MR, setting it to 2 gives me the same
frequency. I also tried setting MR to MCK/16, and got CH0 frequency
to be (187.5/16)KHz.
I'm pretty sure that the internal frequency is set to 48MHz. Although
I can't probe it to be certain, I have the debug uart setup to run at
115200 baudrate to communicate with a PC with no problem. I would
think if my MCK is way off, my uart would be seeing some weird
problems first.
Does anyone have any suggestions on where I should look next? I read
the datasheet a couple of times and didn't find any alternatives to
debug the problem.
Thanks in advance.
Lei
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
I have a strange problem that I would like to get some help on.
My AT91SAM7SE512 processor runs off of a 18MHz crystal and internally
boosts up the master frequency to 48MHz.
When I setup PWM channels, here's what I did:
// enable PWM clock in PMC
pPMC->PMC_PCER = 1 << AT91C_ID_PWMC;
// Enable PWM Output on PIO pins
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA0_PWM0|AT91C_PA1_PWM1, 0);
// Stop the PWM
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0
|AT91C_PWMC_CHID1);
// Set the clock A divider to MCK
AT91C_BASE_PWMC->PWMC_MR = 1;
// Set the Clock
AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA|AT91C_PWMC_CPOL;
AT91C_BASE_PWMC_CH1->PWMC_CMR = MCKtoPWM | AT91C_PWMC_CPOL;
...
At this point I expect to see channel 0 and 1 both have MCK frequency
which should be 48MHz. However, when I probed them on a scope, I'm
getting ~187.5KHz, which is 48MHz/256.
I tried several variants on the MR, setting it to 2 gives me the same
frequency. I also tried setting MR to MCK/16, and got CH0 frequency
to be (187.5/16)KHz.
I'm pretty sure that the internal frequency is set to 48MHz. Although
I can't probe it to be certain, I have the debug uart setup to run at
115200 baudrate to communicate with a PC with no problem. I would
think if my MCK is way off, my uart would be seeing some weird
problems first.
Does anyone have any suggestions on where I should look next? I read
the datasheet a couple of times and didn't find any alternatives to
debug the problem.
Thanks in advance.
Lei
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
Re: PWM master clock problem - v333k - Apr 16 20:40:04 2008
Hi,
I have a suggestion on making sure your internal clock is actually
running at 48MHz. It is not the best suggestion, but I, myself, have
done it this way because I didn't find any other solution.
IF you can enable the SPI and set the clock to 48MHz (divider = 1),
and then probe the SPI clock (you don't need to connect anything to
it), run it in a while loop and let it run infinitely - this should
answer your question.
--- In A...@yahoogroups.com, "birdiezong" wrote:
>
> Hello everyone,
>
> I have a strange problem that I would like to get some help on.
>
> My AT91SAM7SE512 processor runs off of a 18MHz crystal and internally
> boosts up the master frequency to 48MHz.
>
> When I setup PWM channels, here's what I did:
>
> // enable PWM clock in PMC
> pPMC->PMC_PCER = 1 << AT91C_ID_PWMC;
> // Enable PWM Output on PIO pins
> AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA0_PWM0|AT91C_PA1_PWM1, 0);
> // Stop the PWM
> AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0
> |AT91C_PWMC_CHID1);
>
> // Set the clock A divider to MCK
> AT91C_BASE_PWMC->PWMC_MR = 1;
>
> // Set the Clock
> AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA|AT91C_PWMC_CPOL;
> AT91C_BASE_PWMC_CH1->PWMC_CMR = MCKtoPWM | AT91C_PWMC_CPOL;
>
> ...
>
> At this point I expect to see channel 0 and 1 both have MCK frequency
> which should be 48MHz. However, when I probed them on a scope, I'm
> getting ~187.5KHz, which is 48MHz/256.
>
> I tried several variants on the MR, setting it to 2 gives me the same
> frequency. I also tried setting MR to MCK/16, and got CH0 frequency
> to be (187.5/16)KHz.
>
> I'm pretty sure that the internal frequency is set to 48MHz. Although
> I can't probe it to be certain, I have the debug uart setup to run at
> 115200 baudrate to communicate with a PC with no problem. I would
> think if my MCK is way off, my uart would be seeing some weird
> problems first.
>
> Does anyone have any suggestions on where I should look next? I read
> the datasheet a couple of times and didn't find any alternatives to
> debug the problem.
>
> Thanks in advance.
>
> Lei
>
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
I have a suggestion on making sure your internal clock is actually
running at 48MHz. It is not the best suggestion, but I, myself, have
done it this way because I didn't find any other solution.
IF you can enable the SPI and set the clock to 48MHz (divider = 1),
and then probe the SPI clock (you don't need to connect anything to
it), run it in a while loop and let it run infinitely - this should
answer your question.
--- In A...@yahoogroups.com, "birdiezong"
>
> Hello everyone,
>
> I have a strange problem that I would like to get some help on.
>
> My AT91SAM7SE512 processor runs off of a 18MHz crystal and internally
> boosts up the master frequency to 48MHz.
>
> When I setup PWM channels, here's what I did:
>
> // enable PWM clock in PMC
> pPMC->PMC_PCER = 1 << AT91C_ID_PWMC;
> // Enable PWM Output on PIO pins
> AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA0_PWM0|AT91C_PA1_PWM1, 0);
> // Stop the PWM
> AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0
> |AT91C_PWMC_CHID1);
>
> // Set the clock A divider to MCK
> AT91C_BASE_PWMC->PWMC_MR = 1;
>
> // Set the Clock
> AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA|AT91C_PWMC_CPOL;
> AT91C_BASE_PWMC_CH1->PWMC_CMR = MCKtoPWM | AT91C_PWMC_CPOL;
>
> ...
>
> At this point I expect to see channel 0 and 1 both have MCK frequency
> which should be 48MHz. However, when I probed them on a scope, I'm
> getting ~187.5KHz, which is 48MHz/256.
>
> I tried several variants on the MR, setting it to 2 gives me the same
> frequency. I also tried setting MR to MCK/16, and got CH0 frequency
> to be (187.5/16)KHz.
>
> I'm pretty sure that the internal frequency is set to 48MHz. Although
> I can't probe it to be certain, I have the debug uart setup to run at
> 115200 baudrate to communicate with a PC with no problem. I would
> think if my MCK is way off, my uart would be seeing some weird
> problems first.
>
> Does anyone have any suggestions on where I should look next? I read
> the datasheet a couple of times and didn't find any alternatives to
> debug the problem.
>
> Thanks in advance.
>
> Lei
>
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
Re: PWM master clock problem - Johan Ingvast - Apr 17 10:48:29 2008
birdiezong skrev:
> My AT91SAM7SE512 processor runs off of a 18MHz crystal and internally
> boosts up the master frequency to 48MHz.
>
> When I setup PWM channels, here's what I did:
>
> // enable PWM clock in PMC
> pPMC->PMC_PCER = 1 << AT91C_ID_PWMC;
> // Enable PWM Output on PIO pins
> AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA0_PWM0|AT91C_PA1_PWM1, 0);
> // Stop the PWM
> AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0
> |AT91C_PWMC_CHID1);
>
> // Set the clock A divider to MCK
> AT91C_BASE_PWMC->PWMC_MR = 1;
>
> // Set the Clock
> AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA|AT91C_PWMC_CPOL;
> AT91C_BASE_PWMC_CH1->PWMC_CMR = MCKtoPWM | AT91C_PWMC_CPOL;
>
> ...
>
> At this point I expect to see channel 0 and 1 both have MCK frequency
> which should be 48MHz. However, when I probed them on a scope, I'm
> getting ~187.5KHz, which is 48MHz/256.
What have you set the period to. For me it looks like that you have set
the period CPRDx to 256 which should give you 48/256 MHz as you say you
have.
So check CPRDx and possibly CDTYx to see the widht of your pulse.
--
Johan Ingvast, PhD, CEO BioServo Technologies AB
Mob. +46 70 34 34 498 http://www.bioservo.com
Pub. pgp sign.: http://www.md.kth.se/~ingvast/Ingvast_public_key.asc
------------------------------------
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