Greetings to the group,

i've already sent this to the Philips support, but i guess it isn't
hurt to post it here also.

There's something going on at the '931 clock circuirity which makes me
confused.
Our product consists of one base station and from one up to 4000
hand-held terminal units. Base station polls data from hand-held units
via ISM RF link. Property serial communication is used at 38 kbs.
Currently we're not happy with quality of communication as many
retransmits are often required in order to get packet trough. RF
hardware is checked and consequently tuned to maximum performance, but
no avail. It then come to mind that maybe i'm trying to communicate
too fast, as i'm using internal RC oscillator. Perhaps a variation of
CCLK frequency from device to device is cousing misreadings of bit
edges, which leads to reading errors and rejection of packet.
So i took some terminal units and attempt to measure their CCLK freq.
I first try to use clock output option as i have p3.0 free. Didn't get
any output. I tried two methods: to switch bit 6 of  TRIM register by
reading its contents in acc, setting bit 6 of acc and then writing it
back to TRIM, and secondly doing orl TRIM,#1000000B instruction.
Then i wrote small routine, which constits of cpl P3_0, six nop's and
sjmp back to cpl instruction. This suppousedly couses p3.0 pin to
toggle at one 10th of the CCLK. From this i get high/low time of p3.0
to be 2.4 usec, which converts to approx. 4.167 MHz. Huh? Way off
spec. I played with various TRIM register settings and find out that
when TRIM = 0, CCLK = 7.633 MHz and at the other end when TRIM = 63,
CCLK = 4.167 MHz. So, it appears that micro is using a TRIM register
value of 63 at reset. This isn't exactly 7.373 MHz +/- 1% @ 20 C
centigrade. Weird.
I then do a double-check on my findings by using timer1 value. When
terminal responds to poll command, it uses timer1 for bit timer. I
measure transmitted bit times from txd pin and get 27.2 usec. Knowing
that timer1 ticks 88 counts, i figured CCLK to be 6.471 MHz which make
me quite a confused.  If time taken by instructions that get byte into
acc, rotate bit, start timer1, wait it to toggle, reload and loop back
to rotation until 8 bits are rotated is taken into account, that gives
me 7.458 MHz, which isn't clearing things either.
Any idea what's going on here? I must have some deterministic view to
micros clocks in order to evaluate if  it's internal RC osc is
adequate for this product.
I'm using Metalink ASM-51 assembler, KEIL MCB-900 as simulator and
FlashMagic 2.4 with self-made programmer on COM1.

Vesa Koli
	

(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )

vesa_koli wrote:
> Then i wrote small routine, which constits of cpl P3_0, six nop's and
> sjmp back to cpl instruction. This suppousedly couses p3.0 pin to
> toggle at one 10th of the CCLK. 

Label:
   cpl P3.0   ;1
   nop        ;1
   nop        ;1
   nop        ;1
   nop        ;1
   nop        ;1
   nop        ;1
   sjmp Label ;2
           ------
               9 cycles

wek
	

(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )

vesa_koli wrote:
> Then i wrote small routine, which constits of cpl P3_0, six nop\'s and
> sjmp back to cpl instruction. This suppousedly couses p3.0 pin to
> toggle at one 10th of the CCLK. 

Label:
   cpl P3.0   ;1
   nop        ;1
   nop        ;1
   nop        ;1
   nop        ;1
   nop        ;1
   nop        ;1
   sjmp Label ;2
           ------
               9 cycles

wek
	

(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )

vesa_koli wrote:
> That's correct, 've been bit sloppy on my math:) Anyway, this gives
> CCLK frequency to be 3.75 MHz, which is an odd figure in this context.

Hmmmm, and did you consider that the LPC9xx is a two-clocker?

wek

(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )

--- In lpc900_users@lpc9..., Jan Waclawek <wek@...> wrote:
>
> vesa_koli wrote:
> > That's correct, 've been bit sloppy on my math:) Anyway, this gives
> > CCLK frequency to be 3.75 MHz, which is an odd figure in this context.
> 
> Hmmmm, and did you consider that the LPC9xx is a two-clocker?
> 
> wek
>
Well, that was somehow slipped off from my mind. Thank you very much
for straighten things up. I had two erraneus incidents here: first i
somehow forgot that one machine cycle equals two CCLK\'s, and secondly
my oscilloscope that was used in measurements did not have adequate
resolution on its pulse time measuring algorithm. These lead me to the
false conclusions of various timing issues. Now things look to be in
spec. 
BTW, i managed to get CCLK out working by first clearing bit 6 of TRIM
register, and then set it back to 1. A flaw in docuentation, perhaps?

Vesa Koli
	

(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )