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Discussion Groups | LPC900 | I2C SCL Problem Using TR1 Overflow on P89LPC932,3,4 or 5
Find help, specifications and source code for the LPC900. The LPC900 challenges Microchip and AVR based on the worlds most popular 8-bit architecture the 80C51. With a 2-clock core the LPC900 series is a high performance, very flexible and low cost 8-bit microcontroller family. Designers using or interested in these devices are encouraged to share their know-how and ask questions.
I2C SCL Problem Using TR1 Overflow on P89LPC932,3,4 or 5 - poorejw - Jun 15 18:51:47 2007
Using a P89LPC932, 3, 4, or 5, when Timer 1 overflow (Timer 1 in Mode
2) is used as the source for I2C SCL (CRSEL = 1), TH1 determines I2C
SCL rate. I have found that, regardless of microcontroller clock source
or speed, if TH1 is set 253, 254 or 255 then the I2C interface signals
SCL and SDA are not correct (extra SCL pulses and incorrect SDA
levels). If TH1 is set to 252 or below, the I2C interface works
correctly. Unfortunately, I need TH1 to be 254 to get the I2C bus speed
that I need.
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
2) is used as the source for I2C SCL (CRSEL = 1), TH1 determines I2C
SCL rate. I have found that, regardless of microcontroller clock source
or speed, if TH1 is set 253, 254 or 255 then the I2C interface signals
SCL and SDA are not correct (extra SCL pulses and incorrect SDA
levels). If TH1 is set to 252 or below, the I2C interface works
correctly. Unfortunately, I need TH1 to be 254 to get the I2C bus speed
that I need.
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )