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Discussion Groups | LPC900 | ISP to ICP bridge v16
Find help, specifications and source code for the LPC900. The LPC900 challenges Microchip and AVR based on the worlds most popular 8-bit architecture the 80C51. With a 2-clock core the LPC900 series is a high performance, very flexible and low cost 8-bit microcontroller family. Designers using or interested in these devices are encouraged to share their know-how and ask questions.
ISP to ICP bridge v16 - Ingo Debus - Jul 3 7:17:25 2008
Hi all,
(new member here...)
out of curiousity I had a look at the source code of ISP to ICP
bridge v16, available in the files section of this group. It's a bit
funny how the Vdd signal is handled (that switches the supply for the
target LPC9xx on and off).
According to AN10258_2 Vdd is switched on when P2.3 (called VDD in
the source code) of the LPC containing the bridge code is set to high
level. In AN10258_1 it was the other way around.
So in init() Vdd already gets turned on, probably not intended by the
author. In enter_icp() Vdd gets turned off again, even twice. The
second time there's a comment "turn on VDD", but VDD=0 will turn Vdd
off nevertheless.
Then Vdd is turned on by P2 = 0xFF. This again looks as if it's not
intended, the comment here is "release ports".
I take it the v17 source code isn't available anywhere, but meanwhile
I got so curious that I disassembled both v16 and v17. Both init()
and enter_icp() haven't changed in v17. They are just at different
memory locations.
Funny, eh? It seems to me that the hardware has been changed so that
P2.3=1 turns on Vdd rather than off (the difference between AN10258_1
and AN10258_2) to fix a bug in the software. With the AN10258_1
hardware P2 = 0xFF in enter_icp() would switch Vdd off right before
the reset pulses start.
Any comments?
Ingo
------------------------------------
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
(new member here...)
out of curiousity I had a look at the source code of ISP to ICP
bridge v16, available in the files section of this group. It's a bit
funny how the Vdd signal is handled (that switches the supply for the
target LPC9xx on and off).
According to AN10258_2 Vdd is switched on when P2.3 (called VDD in
the source code) of the LPC containing the bridge code is set to high
level. In AN10258_1 it was the other way around.
So in init() Vdd already gets turned on, probably not intended by the
author. In enter_icp() Vdd gets turned off again, even twice. The
second time there's a comment "turn on VDD", but VDD=0 will turn Vdd
off nevertheless.
Then Vdd is turned on by P2 = 0xFF. This again looks as if it's not
intended, the comment here is "release ports".
I take it the v17 source code isn't available anywhere, but meanwhile
I got so curious that I disassembled both v16 and v17. Both init()
and enter_icp() haven't changed in v17. They are just at different
memory locations.
Funny, eh? It seems to me that the hardware has been changed so that
P2.3=1 turns on Vdd rather than off (the difference between AN10258_1
and AN10258_2) to fix a bug in the software. With the AN10258_1
hardware P2 = 0xFF in enter_icp() would switch Vdd off right before
the reset pulses start.
Any comments?
Ingo
------------------------------------
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )