Sign in
Search avrclub
Subscribe to avrclub
avrclub by Keywords
AT90S2313 | AT90S8515 | ATMega | ATmega128 | ECL | FETS | IAR | Keyboard | LCD | STK50 | TMOS | UART
Ads
Discussion Groups
Discussion Groups | AVRclub | [AVR club] now here is a "how come?"
Atmel AVR Microcontroller discussion group.
[AVR club] now here is a "how come?" - Eric Richards - Jul 23 6:27:13 2006
Hi all
How come when you do a "AND" , "OR" , "EOR" when the results is a zero the Z
flag is set
when the result of most significant bit is a 1 then flags S and N are set.
Now there is no "how come" on the about information, it is all very logical.
The "how come" question comes that when you look at the data sheet
(ATmega32) they say flags Z,N,V could be set by the result, (note there is
no mention of flag S)
How come I get flag S to be set and I can not set flag V?
(??? why would you want the "Two's complement overflow indicator" set with
"AND" , "OR" , "EOR" instructions?? )
Am I doing the wrong logic?
Have a great time.
Footnote on status flags reminder:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
How come when you do a "AND" , "OR" , "EOR" when the results is a zero the Z
flag is set
when the result of most significant bit is a 1 then flags S and N are set.
Now there is no "how come" on the about information, it is all very logical.
The "how come" question comes that when you look at the data sheet
(ATmega32) they say flags Z,N,V could be set by the result, (note there is
no mention of flag S)
How come I get flag S to be set and I can not set flag V?
(??? why would you want the "Two's complement overflow indicator" set with
"AND" , "OR" , "EOR" instructions?? )
Am I doing the wrong logic?
Have a great time.
Footnote on status flags reminder:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
Re: [AVR club] now here is a "how come?" - Dave Hylands - Jul 23 10:31:20 2006
Hi,
> The "how come" question comes that when you look at the data sheet
> (ATmega32) they say flags Z,N,V could be set by the result, (note there is
> no mention of flag S)
The AVR Instruction set data sheet indicates that S, V, N, and Z could
be modified, and that S = N xor V.
> How come I get flag S to be set and I can not set flag V?
The AVR Instruction Set data sheet quite explictly says that V will be
set to zero on the AND, OR, and EOR instructions.
Since S = N xor V, and V = 0, then S = N.
> (??? why would you want the "Two's complement overflow indicator" set with
> "AND" , "OR" , "EOR" instructions?? )
> Am I doing the wrong logic?
AND, OR and EOR are bitwise operations so logically there should be no
overflow, which is why V is set to zero.
V being set indicates a loss of information. AND, OR, EOR never lose
any information. The answer is always correct.
However, if you add 128 and 128 you get an answer of 0 with the V bit
set. Since 0 is the wrong answer, there was a loss of information and
the V bit will be set.
--
Dave Hylands
Vancouver, BC, Canada
http://www.DaveHylands.com/
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
> The "how come" question comes that when you look at the data sheet
> (ATmega32) they say flags Z,N,V could be set by the result, (note there is
> no mention of flag S)
The AVR Instruction set data sheet indicates that S, V, N, and Z could
be modified, and that S = N xor V.
> How come I get flag S to be set and I can not set flag V?
The AVR Instruction Set data sheet quite explictly says that V will be
set to zero on the AND, OR, and EOR instructions.
Since S = N xor V, and V = 0, then S = N.
> (??? why would you want the "Two's complement overflow indicator" set with
> "AND" , "OR" , "EOR" instructions?? )
> Am I doing the wrong logic?
AND, OR and EOR are bitwise operations so logically there should be no
overflow, which is why V is set to zero.
V being set indicates a loss of information. AND, OR, EOR never lose
any information. The answer is always correct.
However, if you add 128 and 128 you get an answer of 0 with the V bit
set. Since 0 is the wrong answer, there was a loss of information and
the V bit will be set.
--
Dave Hylands
Vancouver, BC, Canada
http://www.DaveHylands.com/
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
Re: [AVR club] now here is a "how come?" - Eric Richards - Jul 23 14:06:36 2006
You are right Dave
if you ADD 128 & 128 you get flags S,V, Z , C flags set.
How ever if you AND, OR, EOR 128 + 128
Both AND & OR will only set S, N flag
While EOR will only set V
[a repeat of my first Email]
Footnote:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
C is Carry
have a nice day
----- Original Message -----
From: Dave Hylands
To:
Sent: Monday, July 24, 2006 1:43 AM
Subject: Re: [AVR club] now here is a "how come?"
Hi,
> The "how come" question comes that when you look at the data sheet
> (ATmega32) they say flags Z,N,V could be set by the result, (note there is
> no mention of flag S)
The AVR Instruction set data sheet indicates that S, V, N, and Z could
be modified, and that S = N xor V.
> How come I get flag S to be set and I can not set flag V?
The AVR Instruction Set data sheet quite explictly says that V will be
set to zero on the AND, OR, and EOR instructions.
Since S = N xor V, and V = 0, then S = N.
> (??? why would you want the "Two's complement overflow indicator" set with
> "AND" , "OR" , "EOR" instructions?? )
> Am I doing the wrong logic?
AND, OR and EOR are bitwise operations so logically there should be no
overflow, which is why V is set to zero.
V being set indicates a loss of information. AND, OR, EOR never lose
any information. The answer is always correct.
However, if you add 128 and 128 you get an answer of 0 with the V bit
set. Since 0 is the wrong answer, there was a loss of information and
the V bit will be set.
--
Dave Hylands
Vancouver, BC, Canada
http://www.DaveHylands.com/
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
if you ADD 128 & 128 you get flags S,V, Z , C flags set.
How ever if you AND, OR, EOR 128 + 128
Both AND & OR will only set S, N flag
While EOR will only set V
[a repeat of my first Email]
Footnote:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
C is Carry
have a nice day
----- Original Message -----
From: Dave Hylands
To:
Sent: Monday, July 24, 2006 1:43 AM
Subject: Re: [AVR club] now here is a "how come?"
Hi,
> The "how come" question comes that when you look at the data sheet
> (ATmega32) they say flags Z,N,V could be set by the result, (note there is
> no mention of flag S)
The AVR Instruction set data sheet indicates that S, V, N, and Z could
be modified, and that S = N xor V.
> How come I get flag S to be set and I can not set flag V?
The AVR Instruction Set data sheet quite explictly says that V will be
set to zero on the AND, OR, and EOR instructions.
Since S = N xor V, and V = 0, then S = N.
> (??? why would you want the "Two's complement overflow indicator" set with
> "AND" , "OR" , "EOR" instructions?? )
> Am I doing the wrong logic?
AND, OR and EOR are bitwise operations so logically there should be no
overflow, which is why V is set to zero.
V being set indicates a loss of information. AND, OR, EOR never lose
any information. The answer is always correct.
However, if you add 128 and 128 you get an answer of 0 with the V bit
set. Since 0 is the wrong answer, there was a loss of information and
the V bit will be set.
--
Dave Hylands
Vancouver, BC, Canada
http://www.DaveHylands.com/
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
Re: [AVR club] now here is a "how come?" - Eric Richards - Jul 25 13:40:12 2006
It appears that what Atmel call the "S" or Signed flag is called the
"Overflow" in text books
----- Original Message -----
From: Eric Richards
To:
Sent: Sunday, July 23, 2006 10:26 PM
Subject: [AVR club] now here is a "how come?"
Hi all
How come when you do a "AND" , "OR" , "EOR" when the results is a zero the Z
flag is set
when the result of most significant bit is a 1 then flags S and N are set.
Now there is no "how come" on the about information, it is all very logical.
The "how come" question comes that when you look at the data sheet
(ATmega32) they say flags Z,N,V could be set by the result, (note there is
no mention of flag S)
How come I get flag S to be set and I can not set flag V?
(??? why would you want the "Two's complement overflow indicator" set with
"AND" , "OR" , "EOR" instructions?? )
Am I doing the wrong logic?
Have a great time.
Footnote on status flags reminder:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )
"Overflow" in text books
----- Original Message -----
From: Eric Richards
To:
Sent: Sunday, July 23, 2006 10:26 PM
Subject: [AVR club] now here is a "how come?"
Hi all
How come when you do a "AND" , "OR" , "EOR" when the results is a zero the Z
flag is set
when the result of most significant bit is a 1 then flags S and N are set.
Now there is no "how come" on the about information, it is all very logical.
The "how come" question comes that when you look at the data sheet
(ATmega32) they say flags Z,N,V could be set by the result, (note there is
no mention of flag S)
How come I get flag S to be set and I can not set flag V?
(??? why would you want the "Two's complement overflow indicator" set with
"AND" , "OR" , "EOR" instructions?? )
Am I doing the wrong logic?
Have a great time.
Footnote on status flags reminder:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
(You need to be a member of avrclub -- send a blank email to avrclub-subscribe@yahoogroups.com )