You are right Dave
if you ADD 128 & 128 you get flags S,V, Z , C flags set.
How ever if you AND, OR, EOR 128 + 128
Both AND & OR will only set S, N flag
While EOR will only set Z (not V as the last email was)
[a repeat of my first Email]
Footnote:
N is Negative
S is Signed
V is Two's complement overflow indicator
Z is Zero
C is Carry
have a nice day
----- Original Message -----
From: Dave Hylands
To:
Sent: Monday, July 24, 2006 1:43 AM
Subject: Re: [AVR club] now here is a "how come?"
Hi,
> The "how come" question comes that when you look at the data sheet
> (ATmega32) they say flags Z,N,V could be set by the result, (note there is
> no mention of flag S)
The AVR Instruction set data sheet indicates that S, V, N, and Z could
be modified, and that S = N xor V.
> How come I get flag S to be set and I can not set flag V?
The AVR Instruction Set data sheet quite explictly says that V will be
set to zero on the AND, OR, and EOR instructions.
Since S = N xor V, and V = 0, then S = N.
> (??? why would you want the "Two's complement overflow indicator" set with
> "AND" , "OR" , "EOR" instructions?? )
> Am I doing the wrong logic?
AND, OR and EOR are bitwise operations so logically there should be no
overflow, which is why V is set to zero.
V being set indicates a loss of information. AND, OR, EOR never lose
any information. The answer is always correct.
However, if you add 128 and 128 you get an answer of 0 with the V bit
set. Since 0 is the wrong answer, there was a loss of information and
the V bit will be set.
--
Dave Hylands
Vancouver, BC, Canada
http://www.DaveHylands.com/

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