FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Jae Young Hur - Aug 17 2005
Hi
I need some comment from ChipScope Pro users, as I am new to ChipScope Pro VIO. I am using Xilinx ISE 6.3.
Timing simulation after PAR (post place and route) simulation ... 
ramt...@... - Aug 3 2005
Hi
I am looking for some help with the microblaze processor. I need to connect the registers on the microblaze processor to recieve input from the switches on the the boar... 
Jan Gray - Aug 1 2005
I used to take vacation time to attend Hot Chips [hotchips.org] to learn
microprocessor design insights from the greats.
Now I see our own FPGA soft processor community ... 
Jan Gray - Aug 1 2005
I wish to remind our members that messages to this list should be (at least
tangentially) on the subject of COMPUTER DESIGN and COMPUTER ARCHITECTURE
using FPGAs. (The mor... 
smxcu - Jul 31 2005
Hi Everyone,
Does anyone have any tips on getting the Linux port of the Xilinx
software to run on SuSE 9.3 ?
Regards
Sergio Masci
... 
Veronica Merryfield - Jul 22 2005
I wonder if anyone can give me some pointers on this.
Way back when I was at university, I can remember a tutorial on deriving the
optimal number of states per bit for a... 
kris...@... - Jul 8 2005
Hi,
I am trying to drive the VGA display on a ML402 board using EDK7.1i and ISE7.1. I am basically using the ML40x reference design provided by Xilinx.
The problem is that ... 
soytimofonico - Jul 7 2005
Hello,
Here are the two projects that I want to compare and put the
comparison on various forums and mailing lists:
http://c64upgra.de/c-one/s_technical.htm
... 
NeilS - Jun 28 2005
Hello everyone,
Just wondering if anyone has seen or has access to the timing diagrams
for the transactions between a 'classic' Pentium (3.3V core, 75 thru
200MHz) an... 
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