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juendme - Dec 18 2005
The best way to test an FPGA design running on the chip is to use one
of the on-chip analyzers. If you're using Altera's FPGAs, try
Martin Schoeberl - Dec 6 2005
Hi Kolja and all,
>> to get a draft of your spec.
> The draft of the spec at the moment are few sketches on real
> paper - takes some time to draw all diagr...
Martin Schoeberl - Nov 27 2005
After implementing the Wishbone interface for main memory access
from JOP I see several issues with the Wishbone specification that
makes it not the best choice for SoC inte...
a.be...@... - Nov 23 2005
The message cannot be represented in 7-bit ASCII encoding and has been sent as a binary attachment.
ramt...@... - Oct 29 2005
I am looking for some help with the microblaze processor. I need to connect the registers on the microblaze processor to recieve input from the switches on the the boar...
Rob Finch - Oct 12 2005
I have this line of code in my cpu:
wire [DBW*2-1:0] mul_o = opa * opb;
Is there a way I can tell the synthesizer (XST) that I'm allowing two
clock cycles for it to...
Tony - Sep 30 2005
I must have missed the start of your project, what CPU core are you using?
Sounds good ..
On Thursday 29 September 2005 12:25 pm, fpga-cpu@fpga... wrote:
Rob Finch - Sep 30 2005
Dual cpu system...
Got it working I think.
One cpu is constantly updating some characters on the screen, while
the other is running downloads and stuff. The "fun" p...
Umair siddiqui - Sep 29 2005
Please I need your urgent support, related to ACK_I
input of Wishbone bus...
I ve designed a CPU in vhdl (i am trying to release it
with name HPC-16 on OC)
John Kent - Sep 19 2005
Just a notice to anyone playing with the System09 VHDL core,
There are a few updates to the CPU09 core.
JSR [0,S] did not work properly
The stack pointer was pre-dec...