FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Lucian Damoc - May 9 2005
Hello,
I've designed a shifter using only MUXCYs (found in
Xilinx FPGAs). Instead of using the usual 2:1 MUX
(implemented in a LUT), I've used the MUXCY (see the
a... 
Alex Gibson - Apr 24 2005
They now have a virtex2 pro board
http://www.digilentinc.com/info/XUPV2P.cfm
nice academic price of US$299 (industry price of US$1599)
can take up to 2GB of ddr sdram... 
xrisas1 - Apr 23 2005
I'm a student.I'm now learning VHDL. Help.
I'm looking for a generic vhdl library.
Registers,ALU,Shifter,RAM,SubSequencer.
HELP. Implementing CISC architecture... 
Rahul Vishal - Apr 21 2005
Hi everyone,
I am trying to do a post layout simulation. One that is done after the PnR
is over. I have got the Vhdl netlist and also the sdf file. But the
NClaunch ... 
Rob Finch - Apr 9 2005
I'd would like to experiment with multi-processors but I couldn't
think of an application. Then I thought of playing a game of multi-
ball. Would anyone be interested in... 
cationebox - Apr 9 2005
can anyone help me ?
i will use it in my project
but i am not sure to write right code in time
so i turn to you
can you help me ?
vhdl is better than in verilo... 
Rob Finch - Apr 5 2005
I got to thinking about cpu instructions and hardware used to manage
semaphores. Then I got to thinking: why not make a memory with
semaphore operations built in instea... 
Alex Gibson - Apr 5 2005
Spotted this in comp.arch.transputer and in comp.arch.fpga
by johnjakson JJ dated 02/04/2005 (yes 2nd of April)
Announcement
This first partial release date was chos... 
- Apr 5 2005
>
> There was a paper about Hydra in last years FPL conference. I think they
> had an architecture with a processing element per square.
> But apparently a lot of their ... 
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