Sign in
Search fpga-cpu
Subscribe to fpga-cpu
Ads
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Discussion Groups
FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
loop counters [9 Articles]
Rob Finch - Dec 24 2004
One thing that I'd like to see in a cpu is a loop counter. A loop
counter doesn't take hardly any hardware resources, and it can really
offer a performance ben... 
Memory Management [4 Articles]
Rob Finch - Dec 19 2004
What kind of memory management features do the NIOS / Microblaze
offer ? What would be appropriate for SoC systems ?
I've been working on a simple segmented ... Xilinx vs Altera / Microblaze vs Nios??? [14 Articles]
Mats Brorsson - Dec 14 2004
We are in the process of selecting an FPGA board for a series of
laborations in courses ranging from computer engineering, embedded
software development to ... Question about Instruction and Data on an FPGA board
Ben A. Abderazek - Dec 8 2004
Dear Helpers,
I integrated and generated a netlist for a new processor.
I included in the top module two small separate instructions and data memories.
My qu... FPGA Compiler II + Place and Route [23 Articles]
Ben A. Abderazek - Dec 7 2004
Dear Helpers,
I have succeeded to synthesis net list of my processor with FPG compiler II
on a Unix system.
Now when I want to perform "place and route" from ...