This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
I plan to keep the following webpage updated with info on the
Butterfly SoC.
http://www.birdcomputer.ca/Projects/PrjButterflySoC/Butterfly_SoC.html
...
Info on the processor used in my SoC:
http://www.birdcomputer.ca/Cores/Butterfly32_info.html
I have more docs on the way. It just takes time to put ...
Hi all!
I am planning to implement an SMP system on a FPGA.
I want a ready-made core that i can tweak a little for SMP support
and add some glue logi...
I got it working !!!!
An SoC with cpu, video controller, uart, and a few other peripherals.
The cpu is similar in concept to the gr0040's. The full featured ...
The SRAM has a maximum access time of 10 nS and the clock has a period
of 20 nS. That seems a little tight using clk_180 to gate ram_we or
ram_ce.
Could ...