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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
1130 reminiscing [6 Articles]
Jan Gray - Oct 23 2004
Thank you very much for the kind words. Congratulations on your interest in
hands-on computer design.
I too have worked on an 1130, but it doesn't have the same ... 
async SRAM writes [2 Articles]
Jan Gray - Oct 22 2004
> I must have missed the part in the datasheet dealing with asymetric
> timing of read versus write. I have to get back into this as it may
> turn out that my syste... Stack Machine & Memory Bandwidth [20 Articles]
rtstofer - Oct 22 2004
It shouldn't be a surprise that with a stack machine for every
memory fetch there is a consequent stack manipulation. So, we're
looking at 2 memory accesses fo... Questions re: SRAM [5 Articles]
rtstofer - Oct 22 2004
I have been looking at a couple of datasheets for the SRAM I am
using: First, on the Spartan 3 Starter Board is
http://www.issi.com/pdf/61LV25616AL.pdf ... Alpha or Alpha-like processor Verilog code
Ben A. Abderazek - Oct 22 2004
Hello Helpers,
Does any one have or know a Verilog source code of Alpha 21164 (or
Alpha -like) processor?.
Many thanks for your help,
/Ben
UEC, IS, Jap... small CPUs [4 Articles]
Jan Gray - Oct 21 2004
> The XSOC RISC is also not very small.
That stings! Oh well -- de gustibus non disputandem est -- so what's new in
small processor cores? Anyone care to fill in... Floating Point Arithmetic [18 Articles]
rtstofer - Oct 19 2004
I am looking into the design of a processor to implement P4 Pascal.
Since I plan to use the Spartan 3 Starter Board it appears I should
probably design around t... ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor [2 Articles]
sandeep94404 - Oct 15 2004
http://www.niktech.com
Hardware Features
· Data Path Width 32 bits
· Most instructions are 16 bit. PC Relative jump instructions
are 32 bit.
... Pipelined Processor and Buffers [11 Articles]
Ben A. Abderazek - Oct 13 2004
Dear Helpers,
I am implementing an FPGA pipelined processor that is expected to fetch and
execute 2 inst/cycle.
I want to implement buffers to separate eac...