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FPGA-CPU

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

  

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6-bit processor core????

Greg T. - May 24 2004
To whom it may concern, I am a graduate student at Georgia Tech and am taking an adv. VLSI design course. For the class project, I am in need of a 6-bit proc... 6-bit processor core????

How to know the Logic number from FPGA Compiler II ?

Ben A. Abderazek - May 24 2004
Hello, I am using FPGA compiler II to generate net list of a Verilog module. The module can be compiled without any error and I can find the Est. Frequency from the... How to know the Logic number from FPGA Compiler II ?

Re: Question about the STACK size: + Instruction Register

Ben A. Abderazek - May 23 2004
Thank you Towas for the details. I understand it very well and I implement a hardware stack as a first implementation. I do not have so much experience in pro... Re:  Question about the STACK size: + Instruction Register

check out fpgajournal.com

Jan Gray - May 19 2004
You have no doubt noticed the *quiescence* of my old web site, fpgacpu.org. I think you will enjoy and value a relatively new site, fpgajournal.com. I congratula... check out fpgajournal.com

Nios 2 announcements

Jan Gray - May 19 2004
See http://www.altera.com/products/ip/processors/nios2/ni2-index.html. Very interesting. I applaud the spectrum of implementation choices and the D-MIPS one-... Nios 2 announcements

I want to join any RISC processor design in Verilog HDL.   [2 Articles]

Ben A. Abderazek - May 14 2004
Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC processor in Verilog HDL. Regards, /... I want to join any RISC processor design in Verilog HDL.

Question about the STACK size   [3 Articles]

Ben A. Abderazek - May 14 2004
Hello, I want to implement a STACK-Register to support call and interrupt. I am using Verilog HDL. First can I implement it in the processor or it shuold be in ... Question about the STACK size

Adding Instructions and memory-mapped IO devices to xr16

gsamnc - May 13 2004
Can anyone point me to previous posts or docs regarding adding instructions and/or memory-mapped IO devices to the xr16. thanx, greg ... Adding Instructions and memory-mapped IO devices to xr16

Interesting site

Veronica Merryfield - May 7 2004
Found this interesting site today on my meanderings through the World Wide Tangle. I guess some of you have seen it before, but there is some interesting stuff here... Interesting site

High Voltage FPGA   [3 Articles]

kqzca - May 4 2004
Anyone knows any FPGA devices may handle DC voltage higher than 5V, like 24V or higher? Thanks. ... High Voltage FPGA
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