FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Gary Helbig - Jan 30 2004
Another important thing is to make sure the I/O space
does not overlap the processor reset (or interrupt)
vector(s).
G.
--- wrote:
> There is 1 mess... 
vsapre80 - Jan 30 2004
Hello friends,
I wish to know, if any one here knows of any open source program,
that generates bit stream for a vendor device. mostly such programs
are ven... 
Ben A. Abderazek - Jan 29 2004
Hi,
I am trying to select the addresses of several I/O ports ( COM, LPT1, MOUSE,
and VGA) for a new designed processor.
I want first to know, what are the general... 
Ben A. Abderazek - Jan 14 2004
Hi,
I am using Synopsis FPGA compiler II. I want to know how to convert the
"schematic" (when I select "view schematic") to .ps, gif or any other
image file.
Pl... 
shibashish patel - Jan 5 2004
We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain the test-bench written for the sam... 
Anand Gopal Shirahatti - Dec 17 2003
Hi All,
Say I want to build a cycle accurate model of an exisiting processor. Say Intel 386 for example. Now I have access to all the data sheets and plenty of oth... 
Dries Driessens - Dec 8 2003
Dear,
maybe interesting information for people who are new at softcore
processors and busses.
during the course of our research project "embedded system des... 
qfmyue - Dec 2 2003
In Altera development kits ,I can't find the description about it.
The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially,
it has the sliding register ... 
Srinath Bagal V - Nov 17 2003
Hello Group,
I wanted to know the difference between these two books. Which is more
helpful for a hardware student willing to build a small RISC?
Computer Org... 
oridof - Nov 10 2003
Hi,
I am a new graduate student. For research purpose, I need a FPGA
product that has one embedded processor and one coprocessor
consisting of reconfigurable... 
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