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FPGA-CPU

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

  

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GR0040

cybernut999 - Sep 14 2003
Hi Jan I was going over your GR0040 design again and I still think it is one of the most elegant designs on the net - especially for its size. Unfortunately,... GR0040

6809 VHDL Core running   [2 Articles]

John Kent - Sep 4 2003
For those following the Block RAM saga, the answer seems to be that I have my clock edges the wrong way round. I got RAMB4_S8 working as a ROM on my 6800 desig... 6809 VHDL Core running

IDE interface....compact flash   [4 Articles]

yeloohwnala - Sep 2 2003
Hi, Im trying to interface a compact flash card to a Spartan2 FPGA in TrueIDE mode.I am having two main problems 1)My LBA address is being ignored. If I write da... IDE interface....compact flash

User Constraints File - [Was Using Block RAM in Xilinx Spartan2]

John Kent - Aug 31 2003
Hi Thomas, I've tried to include a divide by 4 on my system clock and have fed the output through a Global clock buffer. Problem now is that I am having probl... User Constraints File - [Was Using Block RAM in Xilinx Spartan2]

Using Block RAM in Xilinx Spartan2   [6 Articles]

John Kent - Aug 30 2003
Hi, I've been trying to use Block RAM in some CPU cores I'm designing, using the Xilinx Spartan 2. The CPU designs work fine when I implement the ROM using sli... Using Block RAM in Xilinx Spartan2

ANN: New free soft CPU with tools

fintlewuddlewicks - Aug 20 2003
A free 16-bit CPU is now available at http://www.tinyboot.com/cd16 It includes documentation and tools such as a simulator, optimizing Forth compiler, etc. ... ANN: New free soft CPU with tools

Fwd: Beyond the GFlops per chip   [2 Articles]

Rattus Norvegicus - Aug 11 2003
(Excuse me for my poor english) Mainstream processor cannot provide more than few GFlops per chip, however there are already the technologies needed to create a ... Fwd: Beyond the GFlops per chip

size of RiSC-16 ?

Rob Finch - Aug 8 2003
Hi, Has anyone implemented the RiSC-16 cpu in an FPGA ? And how large was it ? Thanks, Rob ... size of RiSC-16 ?

FPGA DIMM module   [2 Articles]

John Pham - Jul 19 2003
Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600) with ethernet+flash+ram+CPLD. ... FPGA DIMM module

Processor selection   [4 Articles]

Avinash Shetty - Jul 18 2003
Hi Can any one let me know if there is any free open core for a 16 bit processor . I have studied the Picoblaze ....but its just 8 bits and the Microblaze is 3... Processor selection
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