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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
RE: Regarding Xilinx CORE Generator and Mentor FPGA ad v
Jeffery, Robert - Mar 18 2003
Hi Abhishek.
This sort of issue should be dealt with through the software vendor or a
newsgroup that deals with these sorts of issues. The FPGA-CPU group is for ... 
What are peoples opinion of the Altera Nios Processor? [6 Articles]
barrem23 - Mar 17 2003
What kind of problems have you experienced? How was there support?
If you could do it again would you use the NIOS processor?
... string operations [7 Articles]
Rob Finch - Mar 15 2003
Has anyone tried implementing string operations in an FPGA-cpu ? I
roughed it out for a cpu I'm working on (RISC-style) and it seems not
to hard to implement. (It... Regarding Xilinx CORE Generator and Mentor FPGA adv [2 Articles]
abhishek_is_online - Mar 14 2003
Hi,
I want to build some blocks for my modem design using Xilinx cores.
Moreover i am using the FPGA advantage package (VHDL) for designing
my modem. I imported... : UDMA Handling [4 Articles]
Brendan Moran - Mar 13 2003
I hope this isn't too off-topic, but considering the requirements for
attaching a hard drive to most processors, I thought it would be relevant.
I've been tryin... 2. about fpga-cpu (recurring message)
Jan Gray - Mar 13 2003
This is a recurring message on the proper care and feeding of the
fpga-cpu list.
1. Charter and Staying On Topic
"This list is for discussion of the design ... 1. flood of new messages [8 Articles]
Jan Gray - Mar 13 2003
As you know, new members' first posts to this list are moderated. I
have let myself get a couple of weeks behind on that duty -- sorry --
and I just cleared the que... Bit Stream Arithmetic
Sagar Sen - Mar 13 2003
Hi Mr. Jan Gray
I'm trying to implement a systolic array on a Virtex FPGA. The number
of inputs is limited, hence I decided to use deterministic bit stream
a... verilog to vhdl [4 Articles]
eesha_78 - Mar 12 2003
i'm very new in this area. i want to know how to convert from verilog
to vhdl language..for example
assign a= &b[7:0];
assign c= |d[7:0];
when i try to c... Hardware for exception handling [6 Articles]
Rob Finch - Mar 10 2003
Can anyone give me a good reference (URL) to information on hardware
support for exception handling as used in a language like Java or C++.
Thanks,
Rob
...