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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Looking for Lattice XP2 eval board
thilo - May 15 2008
G'day gents,
I'm wondering are there any other lattice XP2 eval boards out?
I found from lattice a 2.5K$ and a 700$ board, but
I would need something not as big as those.
D... 
baud rate devisor [7 Articles]
modeonz007 - May 1 2008
i am using spartan 3e ...i try to communicate with the pc by using
serial communication ..... i use 50 mhz clk ..... i want to get 9600
baud rate to send a 8 bit register .... ... SD card interface using FPGA [4 Articles]
k7ar...@gmail.com - Apr 26 2008
hai all , i am arun . i am working on interfacing SD card using FPGA. i am using SPI mode of communication to SD card .
1. i wrote the code in verilog for the identification mode ... Re: Max CPU speed
thilo - Apr 2 2008
Unless all the processing actually happens inside of a cache (I've seen
intensive multiply loops in 1kb),
this would (under certain instances like the above) make perfect sense... Re: Max CPU speed
Tommy Thorn - Apr 1 2008
--- Rob Finch wrote:
> With 8MB/s of main memory bandwidth,
> What's a reasonable expectation for how fast a CPU
> may operate ?
>
> eg. 80 MHz ?
main memory ban... Re: Max CPU speed
Kolja Sulimma - Apr 1 2008
That depends on your cache architecture and your application.
For some applications you do not care at all about memory bandwidth.
Kolja Sulimma
2008/4/1, Rob Finch :
>
... Frame Grabber using FPGA [2 Articles]
":: aH[sIM] ::" - Mar 22 2008
Hello,
I have decided to use c3088 camera which uses ov6620 from Omnivision on my project. I would like to grab 2 frames into the FPGA.
The camera has VSYNC, HREF, PCLK AND ... interconnection between FPGA and PC [6 Articles]
RANJITH KUMAR REDDY - Mar 22 2008
Hello
Can any one help me regarding how to connect the FPGA to a micro
processor simulator.
I am actually trying to do a project on Using FPGA to implement
Float... Re: Some Looping error i think
John Kent - Mar 22 2008
I'm no expert Sim,
but you are writing VHDL like it is a procedural language.
You should really only have the one clock, say the pixel clock which I
assume is pclk,
then make ... Unable to generate NIOS II [2 Articles]
syyang85 - Mar 6 2008
Hi all,
I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3
development board from Altera.
I'm opening the example of Nios II system made by Altera.
But i ge...