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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Memory Core
Bushra Qamar - Jan 25 2008
Hi.
My next task is to creat memory ..using ip core...i
tried by learing few tutorilas from net but :(
can any one have nice tutorial over it then plz fwd
me...
______... 
how to send image information in to fpga kit [3 Articles]
siva...@gmail.com - Jan 23 2008
hi
I am doing image compression using discrete wavelet
transformation. it is a hard ware implementation . I am using
spartanII fpga kit. But i dont i know how to send image in... Case statement accelerations [2 Articles]
Rob Finch - Jan 18 2008
Just came across this (compiled code for processing switch statements)
// compare case value 1
// jump if eq
// compare case value 2
// jump if eq
// compare case value 3
/... Re: Case statement accelerations
Eric Smith - Jan 18 2008
Rob wrote:
> Just came across this (compiled code for processing switch statements)
> // compare case value 1
> // jump if eq
> // compare case value 2
> // jump if eq
... Frame Grabber using FPGA thru webcam [37 Articles]
syyang85 - Jan 13 2008
Hello,
I'm a student doing a project on implementing optical flow algorithm
into FPGA.
Basically, i would like to mount a camera ( preferably webcam coz its
cheap) onto a FPG... USB/NIOS-II
John Day - Dec 23 2007
Has anybody used the Opencores USB1.1 core on a NIOS-II?
I would be interested in contcting anyone who has.
John
To post a message, send it to: f...@yahoogroups.com
To uns... Strange syntax [13 Articles]
rtstofer - Dec 22 2007
In a project I didn't create there are expressions of the form:
if (atmp+btmp)(8) = '1'
then sr_c_ctrl ... Inferred Priority Encoder In VHDL [11 Articles]
rtstofer - Nov 29 2007
Consider something like:
result ... Re: Inferred Priority Encoder In VHDL [3 Articles]
Charles Steinkuehler - Nov 29 2007
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
rtstofer wrote:
> The Verilog might look like:
>
> assign result = (sig1 ? a : 1'b0) |
> (sig2 ? b : 1'b0) |
> (sig3 ... use C++ int__64 type variables in NIOS IDE [2 Articles]
paria354 - Nov 6 2007
does anyone know how to use C++ int__64 type variables when we want to
implement it on NIOS IDE?
coz IDE doesn't support upper than 32 bit integers.how can we use them
in a bi...