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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "par"
Call for participation in VLSI 2009 in New Delhi.
vlsiconference - Jul 12 2008
Friends,
As you all know, the 22nd conference on VLSI Design would be held in
New Delhi from January 5 to 9th 2009 at The Hotel Taj Palace. The
theme for the conference is "Im... 
Micro16
John Kent - May 1 2008
Hi Richard,
Yes, it was originally intended as a replacement for a state machine to
read a compact flash card.
In the latest version I'm currently working on, I've combined t... Re: Frame Grabber using FPGA
John Kent - Mar 22 2008
Hi Sim
I'm not familiar with Avalon or the SOPC builder whatever that is, so
I'm afraid I cannot assist you with that.
I would like to say that the C3088 camera looks prett... Re: interconnection between FPGA and PC [4 Articles]
artiedc - Mar 10 2008
--- In f...@yahoogroups.com, "RANJITH KUMAR REDDY"
wrote:
>
> Hello
>
> Can any one help me regarding how to connect the FPGA to a
micro
> processor simulator... Unable to generate NIOS II
syyang85 - Mar 5 2008
Hi all,
I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3
development board from Altera.
I'm opening the example of Nios II system made by Altera.
But i ge... Re: how to send image information in to fpga kit
":: aH[sIM] ::" - Feb 4 2008
I am also doing a a somewhat similar project.
I am using the camera C3088 http://instruct1.cit.cornell.edu/Courses/ee476/FinalProjects/s2006/jzs3_da65/jzs3_da65/C3088.pdf
whic... Re: how to send image information in to fpga kit
muhammad yasin - Jan 23 2008
One (CRUDE) way is use UART ...i.e. Serial Port for that
ANother is use Parallel Port instead
Each pixel of the image is byte ... so there's no issue in sending it
........t... Frame Grabber using FPGA thru webcam [16 Articles]
syyang85 - Dec 23 2007
Hello,
I'm a student doing a project on implementing optical flow algorithm
into FPGA.
Basically, i would like to mount a camera ( preferably webcam coz its
cheap) onto a FPG... Strange syntax [7 Articles]
rtstofer - Dec 20 2007
In a project I didn't create there are expressions of the form:
if (atmp+btmp)(8) = '1'
then sr_c_ctrl ... Re: Hirose FX2 Backplane ? [3 Articles]
Leslie - Oct 20 2007
--- In f...@yahoogroups.com, "Rob Finch" wrote:
>
> Is there a Hirose FX2 100 pin backplane or cabling available ?
>
> I'd like to connect some Nexys boards together.
... Re: FPGA routing - was - RE: Re: POP-11 (PDP-11/40 in an FPGA) [3 Articles]
woodelf - Oct 16 2007
Austin Franklin wrote:
> I'm not sure how long it's been since you've done any FPGA work, but though
> that was true up through the 3k and less true with the 4k series of Xil... Inquiry about FPGA and PowerPC codesign
=?GB2312?B?1cXT8dH0?= - Sep 25 2007
Hi all
I am working on Xilinx ML310, with VirtexII pro fpga on it. Now I am trying
to make the FPGA and PowerPC cores(embedded in VirtexII Pro) co-work. For
example, build a f... PDP-11 architecture
Hellwig Geisse - Aug 24 2007
Richard,
I think the following link is highly of interest
when designing the PDP-11 look-alike:
http://research.microsoft.com/~GBell/Computer_Engineering
Especially take ... Suggestions re: Free Tools
rtstofer - Aug 24 2007
The problem with newbies such as myself is that not only don't they
know anything, they don't even suspect!
I have been using WebPack ISE for about 5 years and it has the
adva... Re: POP-11 (PDP-11/40 in an FPGA) [24 Articles]
Scott - Aug 22 2007
Hi,
My PDP-11 VHDL model just passed this very simple test..
So at least a few instructions seem to be working OK.. :-)
Now on to the fun part... implementing the operand
... RE: Paul Metzgen on multiplexers and the NIOS II pipeline [5 Articles]
Goran Bilski - Jul 30 2007
Hi,
Here is how MicroBlaze ALU looks like.
This part of the logic does B+A, B-A, B, A.
The two last could be replaced with something like B and A, B or A but that logic is ... Re: Re: A High Performance 32-bit ALU [2 Articles]
John Kent - Jul 29 2007
Rob,
Wouldn't the synthesis tools optimize the multiplexers ?
If multiplexers were built out of CLBs, the optimum number of inputs
would be 4.
You would not necessarily ga... RE: Re: Microblaze In FPGA Virtex4 ML401? [6 Articles]
Austin Franklin - Jul 21 2007
Hi,
> Microblaze is an IP Core licensed and SOLD by Xilinx. It comes as
> part of their Embedded Development Kit (EDK) and it sells for $900.00.
I believe it's $500, and y... Re: Re: Digilent's Nexys [2 Articles]
Eric Smith - Apr 12 2007
Pedro wrote:
> I can only see 200k and 400k versions of the board...
> I wish that the 1000k board still was available.
They're likely just out of stock of the larger part.
... Re: exclusive access RAM
Thilo Jeremias - Feb 12 2007
That reminds me of an idea intelasys had:
http://www.edn.com/article/CA6334623.html?partner=enews
They essentially block the whole cpu (1 out of many) if it tries to read
fr... BRAM speed [was: Multi-context processor]
Tommy Thorn - Dec 4 2006
I just started playing with Xilinx Spartan 3E (speed grade -4) and I was appalled to find that even with extreme care can I only run the BRAMs at 170 MHz. Anything realistic and th... Oddball bit widths
Rob Finch - Nov 22 2006
I think I found a relatively painless way to handle oddball bit
widths, like 10 bit bytes, 20 bit instruction words, etc. when using
standard memory parts.
I struggled for a... Re: Re: Multi-context processor [3 Articles]
Tobias Gogolin - Nov 9 2006
Does he say he has that?
Or is he proposing?
Its sounds relatively abstract
but if he already implemented that - he's all made...
My idea is more along the programmers model ... [morphware] Low poser going reconfigurable -- Conference announcements
Reiner Hartenstein - Aug 3 2006
Call for Participation:
ISLPED 2006
International Symposium on Low Power Electronics and Design - 2006
October 4-6, 2006, Rottach-Egern, Tegernse... Re: Query on FPGA testing after configure it.
juendme - Dec 18 2005
The best way to test an FPGA design running on the chip is to use one
of the on-chip analyzers. If you're using Altera's FPGAs, try
SignalTap II
( http://www.altera.com/p... Re: Digest Number 782
Tony - Sep 29 2005
I must have missed the start of your project, what CPU core are you using?
Sounds good ..
On Thursday 29 September 2005 12:25 pm, fpga-cpu@fpga... wrote:
>... it breathes - milestone [3 Articles]
Rob Finch - Sep 29 2005
Dual cpu system...
Got it working I think.
One cpu is constantly updating some characters on the screen, while
the other is running downloads and stuff. The "fun" p... Re: 4-read, 4-write* ram [3 Articles]
Brett Wildermoth - Aug 23 2005
I believe he is trying to have a pool of RAM in which four devices can read
and write to at almost the same time. Each device should be able to address
the full capacity o... Question to ChipScope Pro users
Jae Young Hur - Aug 17 2005
Hi
I need some comment from ChipScope Pro users, as I am new to ChipScope Pro VIO. I am using Xilinx ISE 6.3.
Timing simulation after PAR (post place and route) simulation ... Re: Optimal states per bit [5 Articles]
rtstofer - Jul 22 2005
--- In fpga-cpu@fpga..., woodelf Re: Re: Low cost Altera board [2 Articles]
John Kent - Jun 24 2005
Hi Alex,
Alex Gibson wrote:
>John Kent wrote:
>
>
>>I was wondering what size the Altera FPGA is in comparison to the Xilinx
>>devices.
>>
>>
>
>... Parallel Port Programming Of Spartan IIE [3 Articles]
rtstofer - Jun 7 2005
Has anybody seen an app note that shows direct programming of a
Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
intermediate device such as a CPLD?
... Re: Optimal Hardware Implementation FIFO/LRU/Random Algos [2 Articles]
Alex Gibson - Jun 3 2005
invincible1138 wrote:
>Hi all!
>
>I want to know the most optimal way to implement FIFO/LRU/Random in
>hardware. I am designing a cache and i need to implement thes... low cost altera board - US$49
Alex Gibson - May 24 2005
http://www.futureelectronics.com/promos/cyclone/
http://www.futureelectronics.com/promos/cyclone/docs/Cyclone.pdf
No ram and limited peripherals.
Unfilled sp... Help - Shifter using MUXCYs [7 Articles]
Lucian Damoc - May 7 2005
Hello,
I've designed a shifter using only MUXCYs (found in
Xilinx FPGAs). Instead of using the usual 2:1 MUX
(implemented in a LUT), I've used the MUXCY (see the
a... transputer fpga
Alex Gibson - Apr 5 2005
Spotted this in comp.arch.transputer and in comp.arch.fpga
by johnjakson JJ dated 02/04/2005 (yes 2nd of April)
Announcement
This first partial release date was chos... (No subject)
- Apr 5 2005
>
> There was a paper about Hydra in last years FPL conference. I think they
> had an architecture with a processing element per square.
> But apparently a lot of their ... Re: Use for 2 bit opcode ? [3 Articles]
Kolja Sulimma - Apr 2 2005
Rob Finch wrote:
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, bu... messenger discussion on multiprocessors wanted
jyhur63 - Mar 31 2005
dear all
I might want to have a talk and chat about the following issues in
yahoo messenger.
- multiprocessors in fpga
- parallel programming and its tool
...