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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "vliw"
VLIW processors anyone ? [11 Articles]
rtfinch35 - Mar 11 2002
I want to do a VLIW processor in an FPGA, but I'm not confident what
I'm doing. Does anyone have links to sample (educational) VLIW
processor designs ? I've searc... 
VLIW Compiler Help
mycray - Mar 28 2002
I'm wondering on where to get any compiler construction
kits/configurable compilers for VLIW design.
Ali
... Re: Instruction reordering and memory mapped IO
Jason Watkins - Aug 27 2002
Indeed, look at Itanium2. The performance diffence is substancial between I1
and I2, the big changes were:
more memory bandwidth from both bus and cache
2 more... Re: Multiprocessors, Jan's Razor, resource sharing, and all that [3 Articles]
Reinoud - Mar 6 2002
Jan,
This is a beautiful concept! I hope you don't mind a few arguments
against it. :-)
The limitations you claim for uniprocessor design exist only if y... Re: VLIW processors anyone? [2 Articles]
Tommy Thorn - Mar 17 2002
On Sunday 17 March 2002 16:43, Reinoud wrote:
> There are several ways around this. One obvious
approach is
> clustering (a cluster is basically a small VLIW
se... Fwd: Beyond the GFlops per chip [2 Articles]
Rattus Norvegicus - Aug 11 2003
(Excuse me for my poor english)
Mainstream processor cannot provide more than few GFlops per chip,
however there are already the technologies needed to create a ... HyperMTA - On Opencores.org [3 Articles]
mycray - Mar 29 2002
This, is the project that I was asking for compiler help about. I
hope maybe a few people would like to join the project. It is a
multithreaded high end/super com... Re: Use for 2 bit opcode ?
Kolja Sulimma - Apr 2 2005
Rob Finch wrote:
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, bu... Re: CISCifying RISC calls and returns
Johan Klockars - Nov 16 2001
> In the perpetual analysis for, and in striving for the perfect isa,
> it seems to me that cisc style calls and returns would be better than
> than the risc styl... Re: A debugger for xr16 the easy way
- Jul 26 2001
> PS Incidently, I have just come accros a company that do a tool set
> that takes a model view of a processor (register set, instruction
> set definitions) and... Re: Massive parallel graphic processor using FPGA?
- Mar 22 2003
Guillermo:
Yes, this could be done in Xilinx, but still quite expensive.
Maybe less expensive with Spartan3 due soon. VLIW is what you are after.
Trimedia 1500, M... Re: CPU Architectural Question [2 Articles]
Josh Fryman - Jul 29 2001
in short, "no".
in long, this is a non-trivial question. performance always depends
on the underlying application(s) you run. but, to get into specifics
the...