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Discussion Groups | FPGA-CPU | How about writing an FPGA processor with JHDL?

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

How about writing an FPGA processor with JHDL? - Welson Sun - Mar 25 2:16:00 2002


Hi all,

These days, I am looking at JHDL ( http://www.jhdl.org ), although
it seems that there are a lot of issues to be solved itself, the JHDL is
still a good hardware description language. I wonder if there is any
possibility to write an FPGA CPU with JHDL?
Any comments are welcome.

Welson Sun
_________________________________________________________
">http://mail.yahoo.com




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Re: How about writing an FPGA processor with JHDL? - Ben Franchuk - Mar 25 4:48:00 2002

Welson Sun wrote:
>
> Hi all,
>
> These days, I am looking at JHDL ( http://www.jhdl.org ), although
> it seems that there are a lot of issues to be solved itself, the JHDL is
> still a good hardware description language. I wonder if there is any
> possibility to write an FPGA CPU with JHDL?
> Any comments are welcome.
>
> Welson Sun
How portable and open source is JAVA?

--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html





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Re: How about writing an FPGA processor with JHDL? - Simon Gornall - Mar 25 5:24:00 2002

Ben Franchuk wrote:
>
> Welson Sun wrote:
> >
> > Hi all,
> >
> > These days, I am looking at JHDL ( http://www.jhdl.org ), although
> > it seems that there are a lot of issues to be solved itself, the JHDL is
> > still a good hardware description language. I wonder if there is any
> > possibility to write an FPGA CPU with JHDL?
> > Any comments are welcome.
> >
> > Welson Sun
> How portable and open source is JAVA?

Well, you can get the source code for the Linux JVM (2 of them I think
- blackdown and IBM - the blackdown one is the one Sun distribute,
IIRC),
and there is a port of Java to almost every machine I can think of.
Even my 'phone can run Java apps :-)

There's actually a good argument for writing a 'native' Java CPU, except
that some of the core ops are intrinsically non-trivial, from what I
can glean from the FPGA CPU website :-(

As for whether JHDL could be used for a FPGA CPU, you should ask Mike
Butts
(or visit http://www.easystreet.com/~mbutts/xr16vx_jhdl.html)

A question of my own - has anyone (apart from Jan-The-Almighty :-)
ported
lcc to their own FPGA cpu ? I'm struggling at the moment (although
Amazon
still haven't delivered the book yet! Maybe it'll be easier once I've
read that) I realise lcc is *much* simpler than gcc, but it's still a
fairly complex program if you've not been a compiler designer in a
previous life ...

ATB,
Simon





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Re: How about writing an FPGA processor with JHDL? - Martin Schoeberl - Mar 25 5:43:00 2002

From: "Simon Gornall" <>

> There's actually a good argument for writing a 'native' Java CPU, except
> that some of the core ops are intrinsically non-trivial, from what I
> can glean from the FPGA CPU website :-(
>
I'm actually working on it :-) It's running and fits in an Altera ACEX 1K30.
You can find it on www.jopdesign.com.
The JVM instruction set ranges from very simple stack ops to very complex
instructions like invoke a (static) method of an object which can mean to
load a class file (from disc, internet,...) verify it, set up the internal
class structure and than finaly call this method. A practical approach to
this is to build simple instructions in hardware and do the rest in software
(firmware). I even think about writing some complex instructions (like float
ops without hw support) in Java and than call these functions from the JVM.
Strange idea I know :-)

Martin





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Re: How about writing an FPGA processor with JHDL? - Mike Butts - Mar 25 10:50:00 2002

Welson's asking for a CPU written in JHDL. I designed an xr16
for Virtex, and released it under GPL:
http://www.easystreet.com/~mbutts/xr16vx_jhdl.html
JHDL is a super toolset and environment. You'll enjoy it.

--Mike

> These days, I am looking at JHDL ( http://www.jhdl.org ), although
>it seems that there are a lot of issues to be solved itself, the JHDL is
>still a good hardware description language. I wonder if there is any
>possibility to write an FPGA CPU with JHDL?
> Any comments are welcome.
>
>Welson Sun



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Re: How about writing an FPGA processor with JHDL? - Ben Franchuk - Mar 25 13:28:00 2002

Simon Gornall wrote:
> Well, you can get the source code for the Linux JVM (2 of them I think
> - blackdown and IBM - the blackdown one is the one Sun distribute,
> IIRC),
> and there is a port of Java to almost every machine I can think of.

It is the libraries that could be non portable. I would like to see a
linux version
of the latest version of Java and more linux FPGA software.

> A question of my own - has anyone (apart from Jan-The-Almighty :-)
> ported
> lcc to their own FPGA cpu ? I'm struggling at the moment (although
> Amazon
> still haven't delivered the book yet! Maybe it'll be easier once I've
> read that) I realise lcc is *much* simpler than gcc, but it's still a
> fairly complex program if you've not been a compiler designer in a
> previous life ...

The problem I find with C compilers that not very much is written for
smaller machines that will self compile on a low end system. Gcc is ok
if you run linux but what if you want to run dos on a 386 for cheap
development? At the moment I have a cpu design in a fpga but I don't
want to always be tethered to the BIG machine. It does not seem right to
need a P-150 with 64 meg of ram and 1 Gig HD just to download the
program into the FPGA. If I ever get the FPGA cpu design finished it
will have 64K of memory , serial I/O console port , a printer port , a
floppy disk , bootstrap memory , and of course a front panel. Only after
I get the motherboard finished can I get a prom burned for the FPGA and
have it stand alone. Note a high speed design is not needed as my I/O
uses slow chips thus a 4.9152 MHZ clock is more than ample. 800 ns
memory cycle same as XT :)
Most FPGA cpu's don't get past the prototype stage or something
different than a 16 bit RISC,FORTH or STACK machine so I don't expect
large amounts of development software for FPGA cpu's.
PS. I use 'small c' (Version #1) for my FPGA machine developent work.
The software just fits in 24Kb leaving 8Kb for a OS. I hope to fit a
small OS like Flex for the 6800 someday once I get hardware. Note the
problem is not having more than 32Kb of ram on the MOTHERBOARD it is the
fact that the only C compiler I have is DOS based and I can't have more
than 24 kb of emulated memory in the instruction set emulator for my
CPU.
A assembler written in tiny C does make life easyer.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html





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Re: How about writing an FPGA processor with JHDL? - Simon Gornall - Mar 25 19:28:00 2002

Ben Franchuk wrote:
>
> Simon Gornall wrote:
> > Well, you can get the source code for the Linux JVM (2 of them I think
> > - blackdown and IBM - the blackdown one is the one Sun distribute,
> > IIRC),
> > and there is a port of Java to almost every machine I can think of.
>
> It is the libraries that could be non portable. I would like to see a
> linux version
> of the latest version of Java and more linux FPGA software.

Agreed, wholeheartedly, but I don't think that's a library issue. I
use Java (cross platform) daily as my platform of choice. The libraries
are available almost everywhere. Applications may not be. There is
such a thing as the JNI...

For all that Xilinx (to pull a name out of the air :-) has ISE, there
appears to be a fair amount of 'C++' code in it. At least, the
interface doesn't scream 'JAVA' to me... although from what I read,
there is a java component to the suite. I'm not convinced it's a
straight switch, let's put it like that.

<rant>
Personally, the major reason for my limited development time with
FPGA's is that I have to reboot into Windows to do anything. Yes I
know there is a Linux solution. No, I've not managed to make it work
properly (and I've been seriously using linux since 0.13p11 days..)

Almost all of my work these days revolves around Linux rather than
Windows. Most of the time, I have processes running in the background
that I simply don't want to stop. I realise I'm not typical. I also
realise that Xilinx don't have to provide a Linux solution just
because I want one (damn! :-) but I would get a lot more done using
FPGA's rather than commodity parts if they did. I think I'm the
crest of a wave here. Perhaps I'm wrong (it happens :-))
</rant>

I've said it before, and I'll say it again. The current situation
with FPGA's (semi-decent devel tools; easily available parts; pretty
simple learning curve for semi-decent results (no, not guru-level
results, but good-enough results); obvious benefits) is similar to
the s/w boom when people realised they really could "do it themselves".

The limiting factor is whether a similar solution can be architected
in software. Generally, today, it can. The s/w solution is easier,
and frankly more cost-effective in the general case.

Fast forward 5 years (max), and silicon limits are being pushed. All
of a sudden, doing things the elegant way (in h/w) may become more
useful than the brute-force way (in s/w). At the same time, in 5 years
time, the capabilites of FPGA's will be an order of magnitude better
than today. (Look back 5 years to the X 4000 series and consider...)
Think of the capability of having a dozen virtex-2 chips on a single
chip (guesstimate) and what you could do with that. The future is
bright. The future is yours. (I'm still playing catchup :-)

> > A question of my own - has anyone (apart from Jan-The-Almighty :-)
> > ported
> > lcc to their own FPGA cpu ? I'm struggling at the moment (although
> > Amazon
> > still haven't delivered the book yet! Maybe it'll be easier once I've
> > read that) I realise lcc is *much* simpler than gcc, but it's still a
> > fairly complex program if you've not been a compiler designer in a
> > previous life ...
>
> The problem I find with C compilers that not very much is written for
> smaller machines that will self compile on a low end system. Gcc is ok
> if you run linux but what if you want to run dos on a 386 for cheap
> development?

Well, I do run Linux. I don't particularly mind running s/w on a host
to compile for a target (I've been doing that for years, although
FPGA's are relatively new to me :-)

The only problem I have is a limited number of hosts. In fact I'm
probably the wrong way around here :-) Most people probably rejoice
at the choice of Win32 for the development platform. I groan. :-)
It's my cross, and I'll bear it. I don't have to be happy about it
though <grin>

ATB,
Simon (feeling somewhat philosophical :-)


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Re: How about writing an FPGA processor with JHDL? - Jacob Nelson - Mar 25 22:06:00 2002

On Tue, 26 Mar 2002, Simon Gornall wrote:

> Personally, the major reason for my limited development time with
> FPGA's is that I have to reboot into Windows to do anything. Yes I

The command-line Xilinx tools work under Wine. We have been running PARs
this way for a number of months now. As of 4.2i, this is a "supported"
mode of operation.

I haven't tried it at home with the webpack stuff yet, though.

jake




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Re: How about writing an FPGA processor with JHDL? - Sean - Mar 25 22:17:00 2002


Simon,

One piece of advice, run VMware

http://www.vmware.com/

You can have any x86 based os you choose running in a window on your linux
box.

http://www.vmware.com/products/desktop/ws_features.html

Give it a try. I have my eda tools running under nt4 in a window on my unix box.
works great, and instead of shutting down you persist the running VM to disk,
never shutdown your tool instance or reopen your project files again.
Everything just sits right where you left it. Would you need a "save" button if
your computer never shutdown or crashed?

Or you can VNC over to a windows box that can run the tools.

http://www.tightvnc.org/

Multiboot for the most part, is lame.

Sean.

> ATB,
> Simon (feeling somewhat philosophical :-)
>
> To post a message, send it to:
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Re: How about writing an FPGA processor with JHDL? - Simon Gornall - Mar 29 19:45:00 2002

(advice on VMware, Wine, VNC :-)

Thanks for that - I've got VNC running on my machine at the moment, although
I think
I'd like to try the Wine solution out if it frees me from having a powerful
machine running just for FGPA work - this is a hobby after all :-).
I'll give it a go this weekend :-))

Sean wrote:
> Multiboot for the most part, is lame.

Agreed!

A question for all you knowledgeable types... is there a recognised good way
to get multiple bus masters working ? I've got a JPEG-core providing video
to RAM, another 'raw' video feed coming in which needs a frame buffered
in RAM, an audio channel providing 3 channel audio which needs about a
second's buffer, and the CPU wanting access to RAM all at the same time
:-(

I've managed to get (mostly, still struggling a bit with the Jpeg :-) them
all
working in isolation, but now I want to get them tied into a single S2-200,
and if there's a standard sort of way to manage it, I'd love to hear about
it.

ATB,
Simon





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Re: How about writing an FPGA processor with JHDL? - Keith Shapiro - Mar 30 9:56:00 2002

> A question for all you knowledgeable types... is there a recognised good way
> to get multiple bus masters working ? I've got a JPEG-core providing video
> to RAM, another 'raw' video feed coming in which needs a frame buffered
> in RAM, an audio channel providing 3 channel audio which needs about a
> second's buffer, and the CPU wanting access to RAM all at the same time
> :-(

Does your bus provide adequate throughput for all the data you need to
pass? If it does, just make sure you have adequate FIFOs on your inputs
and a short latency timeout so that the FIFOs don't overflow. Some
dataflow analysis should help you get things structured correctly.

You'll just want a good arbitration scheme. The one PCI uses is pretty
good and handles arbitration in a "hidden" fashion so that it doesn't take
up bus time unless the bus is idle. In fact, taking a look at the PCI
spec might not be a bad idea even though it's definitely overkill inside
an FPGA. You'll want to implement the bus as an and-or tree as opposed to
actually using the internal tri-states.. they'll kill your timing and make
routing a bitch.

If that still doesn't meet your bandwidth needs, you'll need to go to a
multi-port RAM interface with each "master" having it's own separate write
and read ports with FIFOs with zero-cycle switching inside the RAM
controller's arbiter.

Keith

--
Keith D. Shapiro

http://www.torilive.org/




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Re: How about writing an FPGA processor with JHDL? - Simon Gornall - Mar 30 10:41:00 2002


----- Original Message -----
From: "Keith Shapiro" <>
To: <>
Sent: Saturday, March 30, 2002 2:56 PM
Subject: Re: [fpga-cpu] How about writing an FPGA processor with JHDL? > > A question for all you knowledgeable types... is there a recognised good
way
> > to get multiple bus masters working ? I've got a JPEG-core providing
video
> > to RAM, another 'raw' video feed coming in which needs a frame buffered
> > in RAM, an audio channel providing 3 channel audio which needs about a
> > second's buffer, and the CPU wanting access to RAM all at the same time
> > :-(
>
> Does your bus provide adequate throughput for all the data you need to
> pass? If it does, just make sure you have adequate FIFOs on your inputs
> and a short latency timeout so that the FIFOs don't overflow. Some
> dataflow analysis should help you get things structured correctly.

Good. I'm pretty sure there's enough bandwidth to go around. The jpeg
stream is only ~150k/sec and the 'raw' video is greyscale @ 1/4 res
and 10 fps, so should be ~300k/sec. It's (currently) an SRAM memory
although that'll probably change to SDRAM in the near future - SRAM
being too expensive with the 2nd video stream... Regardless of the type,
500k/sec (inc audio) + CPU access shouldn't stress it too much.

I've been thinking of using areas of blockram as fifo's to the CPU, and
having the CPU handle all the i/o using a DMA scheme similar to Jan's
original xr16. Dodge the problem, as it were :-) I'm not really using
blockrams for much yet ...

I'm intending to have a blockram CPU cache (i&d) anyway, so assuming
the memory is handled by DMA, and the cache is large enough, it shouldn't
interfere *too* much with the CPU operation...

> You'll just want a good arbitration scheme. The one PCI uses is pretty
> good and handles arbitration in a "hidden" fashion so that it doesn't take
> up bus time unless the bus is idle. In fact, taking a look at the PCI
> spec might not be a bad idea even though it's definitely overkill inside
> an FPGA. You'll want to implement the bus as an and-or tree as opposed to
> actually using the internal tri-states.. they'll kill your timing and make
> routing a bitch.

Cheers, I'll have a look at the spec if I can't get the fifo idea to work
out.

> If that still doesn't meet your bandwidth needs, you'll need to go to a
> multi-port RAM interface with each "master" having it's own separate write
> and read ports with FIFOs with zero-cycle switching inside the RAM
> controller's arbiter.

Nice idea, but far too complex for my liking.

ATB,
Simon.





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