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Discussion Groups | FPGA-CPU | SLL in VHDL

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

SLL in VHDL - Frangline Jose - Apr 1 0:49:00 2002

Hi,
I tried to use SLL, ROR ... in VHDL.

Iam using modelsim for simulation,
Here is the command I used,
vcom -93 shifter.vhd

My code is,
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_STD.all;

ENTITY shifter IS PORT (
clock : IN std_logic;
reset : IN std_logic;
sh_dir : IN std_logic;
--sh_ctl : IN std_logic_vector( 4 DOWNTO 0);
sh_in : IN std_logic_vector(31 DOWNTO 0);

sh_out : OUT std_logic_vector(31 DOWNTO 0)
);
END shifter; ARCHITECTURE behav OF shifter IS
CONSTANT sh_ctl : INTEGER := 2;
BEGIN
PROCESS

BEGIN
WAIT UNTIL clock'EVENT AND clock = '1';
IF reset = '1' THEN
sh_out <= "00000000000000000000000000000000";
ELSE
IF sh_dir = '1' THEN
sh_out <= sh_in SHL 2;
--ELSEIF sh_dir = '0' THEN
--sh_out <= sh_in SLL;
--ENDIF;
END IF;
END IF;
END PROCESS;

END behav; The error is,
ERROR: shifter.vhd(30): near "shl": expecting: ';' Could someone comment on this,

Thanks,
Frang. __________________________________________________






Re: SLL in VHDL - Keith Shapiro - Apr 1 8:48:00 2002


Looks like SLL isn't a recognized VHDL function.

First, your reset is synchronous in this case. Is that what you want?
In an FPGA this generates extra logic in front of the register. There's a
standard global reset line (in xilinx, GSR) routed to every flip-flop in
the part. Also, this reset is usually active low.

Try this:

process (clock, reset_n)
begin
if (reset_n = '0') then
sh_out <= (others => '0');
elsif (clock'event and clock = '1') then
sh_out <= sh_in(29 downto 0) & "00";
end if;
end process;

The above is a not a shift register, however. It's just a register that
chops off the top two bits of a 32-bit word and tacks 0's to the bottom.
However, that's what it appears that your code below is attempting to do.

If you can explain a little more exactly what you're trying to do with
your code, perhaps we can help you more with the VHDL.

Keith On Sun, 31 Mar 2002, Frangline Jose wrote:

> Hi,
> I tried to use SLL, ROR ... in VHDL.
>
> Iam using modelsim for simulation,
> Here is the command I used,
> vcom -93 shifter.vhd
>
> My code is, >
> LIBRARY ieee;
> USE ieee.std_logic_1164.ALL;
> USE ieee.Numeric_STD.all;
>
> ENTITY shifter IS PORT (
> clock : IN std_logic;
> reset : IN std_logic;
> sh_dir : IN std_logic;
> --sh_ctl : IN std_logic_vector( 4 DOWNTO 0);
> sh_in : IN std_logic_vector(31 DOWNTO 0);
>
> sh_out : OUT std_logic_vector(31 DOWNTO 0)
> );
> END shifter; > ARCHITECTURE behav OF shifter IS
> CONSTANT sh_ctl : INTEGER := 2;
> BEGIN
> PROCESS
>
> BEGIN
> WAIT UNTIL clock'EVENT AND clock = '1';
> IF reset = '1' THEN
> sh_out <= "00000000000000000000000000000000";
> ELSE
> IF sh_dir = '1' THEN
> sh_out <= sh_in SHL 2;
> --ELSEIF sh_dir = '0' THEN
> --sh_out <= sh_in SLL;
> --ENDIF;
> END IF;
> END IF;
> END PROCESS;
>
> END behav; > The error is,
> ERROR: shifter.vhd(30): near "shl": expecting: ';' > Could someone comment on this,
>
> Thanks,
> Frang. > __________________________________________________
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
>
> ">http://docs.yahoo.com/info/terms/

--
Keith D. Shapiro

http://www.torilive.org/



_____________________________
 Free pdf download: Introduction to Embedded Systems.


Re: SLL in VHDL - Jeffery, Robert - Apr 2 4:47:00 2002

Hi Frang.

Your codes isn't working because the SHL isn't a VHDL construct and doesn't
exist in the packages you are using. In the basic language you have:

SLL, SRL, SLA, SRA, ROL and ROR. These are in 93 not in 87. They are
procedures so they get called as:

SLL(arg1, arg2) where arg1 is a 1-D array of bit or boolean and arg2 is an
integer.

Note SLL is shift logical left and SLA is shift arithmetic left!

Now you have used the NUMERIC package. This supports signed and unsigned
types NOT std_logic_vector. You can convert using the conversions signed and
unsigned if you want to. You would then need to use the NUMERIC_STD shift
operators eg. shift_left, shift_right.

So your code would like the following:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;

ENTITY shifter1 IS PORT (
clock : IN std_logic;
reset : IN std_logic;
sh_dir : IN std_logic;
sh_ctl : IN natural range 0 to 32;
sh_in : IN unsigned (31 DOWNTO 0);
sh_out : OUT unsigned (31 DOWNTO 0)
);
END shifter1;
ARCHITECTURE behav OF shifter1 IS

BEGIN

PROCESS

BEGIN
WAIT UNTIL clock'EVENT AND clock = '1';
IF reset = '1' THEN
sh_out <= "00000000000000000000000000000000";
ELSIF sh_dir = '1' THEN
sh_out <= SHIFT_LEFT(sh_in, sh_ctl);
ELSE
sh_out <= SHIFT_RIGHT(sh_in, sh_ctl);
END IF;

END PROCESS;

END behav;

Alternatively if you really wanted to use SHL and SHR then you need to use
the std_logic_arith package which has the operators SHL, SHR but again you
will need to convert the types!

So your code would like the following:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;

ENTITY shifter IS PORT (
clock : IN std_logic;
reset : IN std_logic;
sh_dir : IN std_logic;
sh_ctl : IN std_logic_vector ( 4 DOWNTO 0);
sh_in : IN std_logic_vector (31 DOWNTO 0);
sh_out : OUT std_logic_vector (31 DOWNTO 0)
);
END shifter;

ARCHITECTURE behav OF shifter IS
BEGIN

PROCESS

VARIABLE temp : unsigned (31 DOWNTO 0);

BEGIN
WAIT UNTIL clock'EVENT AND clock = '1';
IF reset = '1' THEN
sh_out <= "00000000000000000000000000000000";
ELSIF sh_dir = '1' THEN
temp := SHL(UNSIGNED(sh_in), UNSIGNED(sh_ctl));
ELSE
temp := SHR(UNSIGNED(sh_in), UNSIGNED(sh_ctl));
END IF;

sh_out <= CONV_STD_LOGIC_VECTOR(temp, 32);

END PROCESS;

END behav;

I have synthesised the latter for a Virtex v50bg256 6 speed grade. the
result was:

***********************************************
Device Utilization for v50bg256
***********************************************
Resource Used Avail Utilization
-----------
IOs 73 180 40.56%
Function Generators 312 1536 20.31%
CLB Slices 156 768 20.31%
Dffs or Latches 32 1536 2.08%

and post PAR of 100MHz.

Qualis Design Corporation have a great 1164 packages quick reference card
that you can download from their site. You need to signup to their library
and then you can access it. It's free and there's lots of good things in
there! Check it out at www.qualis.com

Cheers.

Robert.

----
--------

Robert Jeffery. Principal Regional Applications Engineer
Mentor Graphics (UK) Ltd
Melbourn
Royston
SG8 6HB
HERTS

Telephone +44 1763 264950
Direct Dial +44 1763 264953
Mobile +44 7836 224397
Fax +44 1763 263312
http://www.mentor.com/ Global Web site
http://www.mentor.com/uk Regional Web site
----
--------

-----Original Message-----
From: Frangline Jose [mailto:]
Sent: Monday, April 01, 2002 6:49 AM
To:
Subject: [fpga-cpu] SLL in VHDL Hi,
I tried to use SLL, ROR ... in VHDL.

Iam using modelsim for simulation,
Here is the command I used,
vcom -93 shifter.vhd

My code is,
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_STD.all;

ENTITY shifter IS PORT (
clock : IN std_logic;
reset : IN std_logic;
sh_dir : IN std_logic;
--sh_ctl : IN std_logic_vector( 4 DOWNTO 0);
sh_in : IN std_logic_vector(31 DOWNTO 0);

sh_out : OUT std_logic_vector(31 DOWNTO 0)
);
END shifter; ARCHITECTURE behav OF shifter IS
CONSTANT sh_ctl : INTEGER := 2;
BEGIN
PROCESS

BEGIN
WAIT UNTIL clock'EVENT AND clock = '1';
IF reset = '1' THEN
sh_out <= "00000000000000000000000000000000";
ELSE
IF sh_dir = '1' THEN
sh_out <= sh_in SHL 2;
--ELSEIF sh_dir = '0' THEN
--sh_out <= sh_in SLL;
--ENDIF;
END IF;
END IF;
END PROCESS;

END behav; The error is,
ERROR: shifter.vhd(30): near "shl": expecting: ';' Could someone comment on this,

Thanks,
Frang. __________________________________________________

To post a message, send it to:
To unsubscribe, send a blank message to: ">http://docs.yahoo.com/info/terms/