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Discussion Groups | FPGA-CPU | 1:00 am designing.

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

1:00 am designing. - Ben Franchuk - Apr 10 2:00:00 2002

It is now 1:00 am and I was wondering about using a PLD to clean up some
random logic. Does anybody know of a easy programmer for the EEPROM
based PLD's (not pals) since I am replacing TTL here and a $1000
programer is out of the question for a few TTL chips?

--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html


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Re: 1:00 am designing. - Eric Smith - Apr 10 4:58:00 2002

> It is now 1:00 am and I was wondering about using a PLD to clean up
> some random logic. Does anybody know of a easy programmer for the
> EEPROM based PLD's (not pals) since I am replacing TTL here and a $1000
> programer is out of the question for a few TTL chips?

I don't know of one. But a lot of the recent CPLDs can be programmed with
JTAG or other serial interfaces, without the need for special programming
voltages, so it is possible to hook them up to a PC parallel port and use
software from the vendor to program the parts.

The Cypress CY37000 family parts are fairly inexpensive, and can be ordered
online from Arrow. The Cypress CY3620 eval kit costs $175 from Cypress'
online store, and includes a demo board with a CY37256 (256-macrocell)
and a Delta39K family CY39100 (1536 macrocells and embedded RAM) [*], the
WARP software for VHDL and Verilog synthesis, and the ISR programming
cable. You can get the software alone for $99 if you just want to build
your own board and cable.

Other vendors have similar deals.

Eric

[*] Back when I bought mine, the Delta 39K family wasn't yet available,
so the board had a second footprint for a 37K part. I installed a
CY37512 (512 macrocell) on mine.





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Re: 1:00 am designing. - Ben Franchuk - Apr 10 9:44:00 2002

Eric Smith wrote:

> I don't know of one. But a lot of the recent CPLDs can be programmed with
> JTAG or other serial interfaces, without the need for special programming
> voltages, so it is possible to hook them up to a PC parallel port and use
> software from the vendor to program the parts.

I may look into a JTAG homebrew cable.

> The Cypress CY37000 family parts are fairly inexpensive, and can be ordered
> online from Arrow. The Cypress CY3620 eval kit costs $175 from Cypress'
> online store, and includes a demo board with a CY37256 (256-macrocell)
> and a Delta39K family CY39100 (1536 macrocells and embedded RAM) [*], the
> WARP software for VHDL and Verilog synthesis, and the ISR programming
> cable. You can get the software alone for $99 if you just want to build
> your own board and cable.

I got Altera software for the 10K10 FPGA I am programing. I may go with
a 64 or 128? macrocell device but if I use JTAG configuration I want to
have all the information on programing the device in case I want to
something other than a windows/intel computer.

--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html


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Re: 1:00 am designing. - Christian Plessl - Apr 10 10:19:00 2002

> I got Altera software for the 10K10 FPGA I am programing. I may go with
> a 64 or 128? macrocell device but if I use JTAG configuration I want to
> have all the information on programing the device in case I want to
> something other than a windows/intel computer.

You might also consider Xilinx CPLDs. The programmer costs 99$ at Xilinx
webshop, or you could build your own cable. The software Xilinx Webpack
is also free (free as in free beer) but only available for Windows.

Regards,
Chris




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simulator - Alessandro Noriaki Ide - Apr 11 8:56:00 2002



Does anybody knows some simulator software to simulate a reconfigurable
architecture ? And enables me to mesure its performance ?I mean some
simulator which uses a high level language instead of a HDL ?

thanks,
Nori




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