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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

RE: Bus Arbitation - Perez Ramas, Javier Basilio - Apr 18 1:39:00 2002


Hi,

> --VHDL provides a lot of constructs that will simulate
> correctly but have no
> --hardware instantiation. You're using integer concepts like
> '>' and '<'
> --and expecting them to map correctly into hardware.
>
> I would have expected the my synthesis tool to convert my constructs
> to represent them in hardware. I can easily replace statments like
> count > 0 with (if (count and "0000") = '1' )

If you include the proper library files the synthesis engine should have hardware schemes to implement these operators. For example:

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

in Synopsys must be enough to use these operators, allowing constructions as

if (counter<="11011") then
your code
end if

Bye
Jaba





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