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I am relatively a novice with respect to the other
memebers of this group,so pardon my ignorance if you
I am having a slight problem with synthesis in VHDL.
well i want to put the tri-state code in my design,and
i did that with the "NULL'statement( I hope that is
but with my Synplify tool,it gives me an error in
VHDL STD package and stating " CANNOT ASSIGN TYPE TO
now i included the IEEE.std library in my file..
i have a feeling that I may have to include another
well can you people help me out with this problem of
thank you __________________________________________________
HI,Null is jus to indicate that u don't do anything,it|
practically makes no sense and all syn tools will give
that the null case is not selected for synthesis
foe modelling a tri state:
If (enable = '1') then
y_out <= x_in;
y_out <= 'Z';
this will do.Hope this will be some help.