Sign in

username or email:

password:



Not a member?
Forgot your Password?

Search fpga-cpu



Search tips

Subscribe to fpga-cpu



Discussion Groups

See Also

DSPFPGA

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).


So far in May, you have voted 0 times ou of a total of 20 votes by the community.
Please help us clean the archives from unuseful discussion threads by using the voting system! Details here.


Is this thread worth a thumbs up?

0

- Mayukh Mukherjee - Apr 22 1:52:00 2002

hello!!
I am relatively a novice with respect to the other
memebers of this group,so pardon my ignorance if you
can..
I am having a slight problem with synthesis in VHDL.
well i want to put the tri-state code in my design,and
i did that with the "NULL'statement( I hope that is
correct)
but with my Synplify tool,it gives me an error in
VHDL STD package and stating " CANNOT ASSIGN TYPE TO
NULL"..
now i included the IEEE.std library in my file..
i have a feeling that I may have to include another
package ..
well can you people help me out with this problem of
mine..

thank you __________________________________________________






(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Re: (unknown) - Bala Subramani.C - Apr 22 3:39:00 2002

HI,Null is jus to indicate that u don't do anything,it
practically makes no sense and all syn tools will give
that the null case is not selected for synthesis
foe modelling a tri state:

x_in-----------|\---------y_out
|/
enable----------|

If (enable = '1') then
y_out <= x_in;
else
y_out <= 'Z';
end if;
this will do.Hope this will be some help.
Bala.C

__________________________________________________





(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )