This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
|
hello!! I am relatively a novice with respect to the other memebers of this group,so pardon my ignorance if you can.. I am having a slight problem with synthesis in VHDL. well i want to put the tri-state code in my design,and i did that with the "NULL'statement( I hope that is correct) but with my Synplify tool,it gives me an error in VHDL STD package and stating " CANNOT ASSIGN TYPE TO NULL".. now i included the IEEE.std library in my file.. i have a feeling that I may have to include another package .. well can you people help me out with this problem of mine.. thank you __________________________________________________ |
|
|
|
HI,Null is jus to indicate that u don't do anything,it practically makes no sense and all syn tools will give that the null case is not selected for synthesis foe modelling a tri state: x_in-----------|\---------y_out |/ enable----------| If (enable = '1') then y_out <= x_in; else y_out <= 'Z'; end if; this will do.Hope this will be some help. Bala.C __________________________________________________ |