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Discussion Groups | FPGA-CPU | YARD-1A processor size
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
YARD-1A processor size - Brian Davis - Sep 25 22:17:00 2000
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Hello all, Here's some information re. the YARD-1A processor size; slice counts are for the entire chip, including core, memory, and I/O ports. 16 bits : 270 slices ( 22% of an XC2S100, 63% of an XC2S30 ) 32 bits : 458 slices ( 38% of an XC2S100 ) I haven't modified the instruction ROM to use the Spartan-II block RAM yet, which would remove 64 16x1 ROMS and some associated mux logic from the design. Brian Davis MAP report snippets: 16 bit core, 64x16 instruction ROM, 32x16 data RAM, 8 bit I/O port: Target Device : x2s100 Target Package : pq208 Target Speed : -5 Mapper Version : spartan2 -- C.18 Mapped Date : Mon Sep 25 22:57:10 2000 Design Summary -------------- Number of errors: 0 Number of warnings: 4 Number of Slices: 270 out of 1,200 22% Slice Flip Flops: 106 4 input LUTs: 335 Dual Port RAMs: 16 32x1 RAMs: 16 16x1 RAMs: 29 16x1 ROMs: 64 Number of Slices containing unrelated logic: 0 out of 270 0% Number of bonded IOBs: 50 out of 140 35% Number of Tbufs: 160 out of 1,280 12% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% 32 bit core, 64x16 instruction ROM, 32x32 data RAM, 8 bit I/O port: Target Device : x2s100 Target Package : pq208 Target Speed : -5 Mapper Version : spartan2 -- C.18 Mapped Date : Mon Sep 25 22:29:26 2000 Design Summary -------------- Number of errors: 0 Number of warnings: 4 Number of Slices: 458 out of 1,200 38% Slice Flip Flops: 170 4 input LUTs: 579 Dual Port RAMs: 32 32x1 RAMs: 32 16x1 RAMs: 45 16x1 ROMs: 64 Number of Slices containing unrelated logic: 0 out of 458 0% Number of bonded IOBs: 50 out of 140 35% Number of Tbufs: 384 out of 1,280 30% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% |
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