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Discussion Groups | FPGA-CPU | RE: format of the Xilinx bit file
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
format of the Xilinx bit file - stuckatone - May 8 9:26:00 2002
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I searching for any info on how to decode the "raw data" in the bit file which is created from the Xilinx Foundation software package. I have successfully found info on the header fields but I can't find anything on the "raw data" section which is used to progrm the FPGA. Any information on a 2-input OR gate and a 2-input AND gate would be great. Mike |
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RE: format of the Xilinx bit file - Aare Tali - May 11 19:48:00 2002
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> -----Original Message----- > From: stuckatone [mailto:] > Sent: Wednesday, May 08, 2002 9:26 AM > To: > Subject: [fpga-cpu] format of the Xilinx bit file > I searching for any info on how to decode the "raw data" in the bit > file which is created from the Xilinx Foundation software package. > > I have successfully found info on the header fields but I can't find > anything on the "raw data" section which is used to progrm the FPGA. For Virtex you can request JBits package from Xilinx, subscribe to JBits group on Yahoo and start digging in information you get from there. JBits is primarily used to modify configuration bitstreams but still, every bit you can change is indirectly documented by data structures in the package. XC4000 series JBits was available before they ported it to Virtex (not E, EM, not 2, not 2PRO, just plain Virtex and Spartan-2), but I haven't seen it. Check out their answer 8484. |
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Re: format of the Xilinx bit file - Philip Freidin - May 12 1:03:00 2002
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On Wed, 08 May 2002 14:26:05 -0000, MIKE wrote: >I searching for any info on how to decode the "raw data" in the bit >file which is created from the Xilinx Foundation software package. You cant. The details are proprietary, and there is no reason to expect Xilinx to change this. You can read ENDLESS (and pointless) discussions by going through the archive of comp.arch.fpga, at http://www.fpga-faq.com/archives and enter a search phrase of "bitstream format" , including the quotes. >I have successfully found info on the header fields but I can't find >anything on the "raw data" section which is used to progrm the FPGA. And you wont. >Any information on a 2-input OR gate and a 2-input AND gate would be >great. These are buried within a LUT, and so even such low level stuff is encoded. You can for example though, use the FPGA editor to create a trivial design with 1 AND gate, and create a bitstream, then change the AND gat to a OR gate, and create another bitstream. Then you could diff the two bitstreams. The common wisdom, is if you really want to dink with the bitstream, you should use the special tools Xilinx has created for this, called JBITS. Search the FAQ to see what others have said about this. >Mike Philip ================= Philip Freidin |
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Re: format of the Xilinx bit file - Reinoud - May 12 6:45:00 2002
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Philip Freidin <> wrote: > You can read ENDLESS (and pointless) discussions by going through the > archive of comp.arch.fpga, at http://www.fpga-faq.com/archives and > enter a search phrase of "bitstream format" , including the quotes. Graham Seaman has made a nice summary of one of the better threads on this subject: http://opencollector.org/news/Bitstream/ BTW, check out his excellent site about open hardware and design software (http://opencollector.org/). - Reinoud |
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Re: format of the Xilinx bit file - Mukti Bansal - May 20 6:54:00 2002
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Can you pl give me any information about the header file?? Actually even i am trying to find out exactly what data is stored in the bit file or if you know how can we read the bit file?? Mukti --- stuckatone <> wrote: > I searching for any info on how to decode the "raw > data" in the bit > file which is created from the Xilinx Foundation > software package. > > I have successfully found info on the header fields > but I can't find > anything on the "raw data" section which is used to > progrm the FPGA. > > Any information on a 2-input OR gate and a 2-input > AND gate would be > great. > > Mike > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > __________________________________________________ |
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