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Discussion Groups | FPGA-CPU | Regarding the core-gen

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Regarding the core-gen - Vikram Chandrasekhar - Jun 8 19:44:00 2002


Hello all,
I am trying to use an IP-CORE Virtex multiplier block for my design.

The CORE GEN is targetted to a Virtex-2 FPGA, has an output latency of
4 cycles, uses triangular packing, has input widths of 16 bits(signed),
and an output width of 32 bits(signed).

I obtain a maximum clocking frequency of 164.853 Mhz on
instantiating a single multiplier.
On instantiating a bank of 8 multipliers (in parallel),
the max. clocking frequency drops to 83.8 Mhz.

1).Why is there such a large drop in the max. clocking frequency?

2).Is there any special way for generating multiple
instances of a IP core or can it be treated like any other component
instantiation?

3). Should any constraints be placed while generating multiple instances
of IP-cores?

Thanks
Vikram



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