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Discussion Groups | FPGA-CPU | Request for testers: SFL to Verilog converter
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Request for testers: SFL to Verilog converter - N S - Jun 15 19:30:00 2002
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Hi, I wrote a SFL to Verilog converter program. The package is downloadable from my home page. The package has m65(6502 compatible), mz80( z80 semi-compatible) processors for test. The target Verilog compiler is now Icarus Verilog. Because I am not so familiar with Verilog, I need people to help me testing the program. At now, there are some problems about bidirectional terminal, memory and power on reset vector. I have the patch but I don't update the package yet. (It is relatively a small problem for IP core design.) Anyone who can help me, please visit: http://shimizu-lab.dt.u-tokai.ac.jp/indexe.html Regards, Naohiko Shimizu __________________________________________________ |
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