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Discussion Groups | FPGA-CPU | Re: Re: YARD-1A Consts, CCs, Skips

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Re: Re: YARD-1A Consts, CCs, Skips - Ben Franchuk - Sep 29 10:35:00 2000

Philip Freidin wrote:
>
> On Fri, 22 Sep 2000 02:39:20 -0000, you (Brian Davis) wrote:
> >Philip,
> > Is any of the RISC4005 stuff online?

Hey I am having trouble downloading the YARD-stuff.

> No. My design and Jan's XR16 are very similar, only he has done a
> far better job of documenting it, and supporting it with software.
> Jan's work, while independent of mine had many striking similarities
> to the RISC4005, which we realized when we started trading email
> and phone calls a few years ago.

That is not surprising,since you only have only a few ways to layout the
opcodes.
Or is it GREAT MINDS think alike.

> We agreed that this was probably due to both of us having the same
> basic goals of efficient implementation, and realizing that an efficient
> CPU would be far better if the CPU architecture was adjusted to the
> FPGA resources, rather than a standard CPU, with the FPGA resources
> applied to meet an existing architecture.

I think that FPGA's architecture for LOAD/STORE designs is just a
lucky accident. FPGA logic clusters in clumps of logic that happens
to make highly pipelined designs easy. I guess there is 4:1 speed
difference between the logic block and a individual transistor/logic gate.
If you had a Gate array chip that was programmable using a ECL OR/NOR
logic you might have a different design style.

> > ( I built a 40 bit bit-slice machine, sorta like a lobotimized
> >'2901, in a 4010 when they first came out in the 92-93 timeframe.
> >Had 16 general registers, 16 constant registers, external '448
> >microsequencer; it ran at 12.5 MHz, with a 25 MHz clock to generate
> >the then-required asynchronous CLB write signal )
>
> I have in my garage a variable width data path microcoded CPU, built
> in 1980-1982 with 8 x 2903s, and a very modified 2910. It covers about
> twenty 6U by 220mm wire wrap cards. It includes 128 bit wide microword,
> with up to 1 MW of control store, all built with 4Kbit SRAMs (8KW
> implemented, and VM (yes, VM microcode) for the rest. I/O channel is
> dual 16 bit Multibus 1 cardcages. The boot processor was an 8080 CPM
> system that booted a custom Z8000 system (I designed this too, and the
> OS on it), and the Z8000 then loaded the WCS, and controlled the clocks
> for the system.

Boo -- No micro code ... Go TTL logic.:)
I think that is the place for VM is in micro code or hard logic.
Most OS's spend too much time doing things hardware needs to do.
I think I/O Hardware needs to be DUMB but fast with the right
amount of functionality on the external device.

> >>A really neat capability of RISC4005 (that I should have patented,
> >>because no-one before or after me has thought of it) was the stunning
> >>additional instruction group: SKIP2, of which I had 48 of these as well.
> >>It skipped 2 instructions. Which is great for double precision arith,
> >>because you can skip an ADD, and an ADDC (add with carry) with
> >>one skip instruction. This really helps in multiply and divide
> >routines.

The PDP-10 may have had that too, as I know it has a wide range of skips.
(I am a PDP-8 user and it only had the one skip style )

The only place I could see a skip like that being handy
is in a divide loop. CMP A,B CMPB C,D SN2 SUB A,B SBB C,D.
But you have a divide step instruction right?

> I of course stand corrected, and humbled :-)

> > I also had my own "skip extension" plans for the 5 opcode bits
> >that are now in use for the bit number of the "skip on bit" mode:
> >
> > SMODE : selects AND or XOR of skip condition with enable bits
> >
> > E1 : enable for first instruction following skip
> > E2 : enable for second
> > E3 : enable for third
> > E4 : enable for fourth
>
> This sounds pretty neat. Have you thought how you will get a compiler
> to make use of this?
>
> > In the AND mode, the instructions with enable bits set are skipped
> > if the condition was true, executed if the condition was false;
> > those with enable bits cleared are executed normally.
> >
> > In the XOR mode, the instructions with enable bits set are skipped
> > if the condition was true, executed if the condition was false;
> > instructions with enable bits cleared suffer the opposite fate.

Sounds like the PDP-8 skip style ... Mode 1 Conditions are ANDED together
Mode 2 Conditions are ORED together.

> >
> > ( If I don't implement short conditional branches, I may bring this
> > back as an "eskip" instruction using what's now the "br.cc" opcode )
> >
> > This won't work on the 16 bit datapath processor, as there aren't
> > enough bits in the status register to hold the four pending bits of
> > skip state.
> >
> >
> >still having fun,
> >Brian Davis
>
> Me too.

Give my time to have fun too... I am still assembling
my FPGA kit.

Ben.
--
"We do not inherit our time on this planet from our parents...
We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk


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Re: Re: YARD-1A Consts, CCs, Skips - Ben Franchuk - Sep 29 13:43:00 2000

Brian Davis wrote:
>
> --- In , Ben Franchuk <bfranchuk@j...> wrote:
>
> >Hey I am having trouble downloading the YARD-stuff.
>
> I checked from a few computers at work and home, it
> seems to be there... I did notice that one web browser
> didn't show the file when looking at the ftp site, although
> if you clicked on or typed the whole link it would download
> it OK. Maybe try it with a FTP program instead of your
> browser?

AOL and my linux box does not get along.I tried to get it with
two different FTP programs and no luck. The only reason I still
have windows around is to run the (Altera) FPGA software.
Ben.
--
"We do not inherit our time on this planet from our parents...
We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk





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Re: YARD-1A Consts, CCs, Skips - Brian Davis - Sep 29 21:22:00 2000

--- In , Ben Franchuk <bfranchuk@j...> wrote:

>Hey I am having trouble downloading the YARD-stuff.

I checked from a few computers at work and home, it
seems to be there... I did notice that one web browser
didn't show the file when looking at the ftp site, although
if you clicked on or typed the whole link it would download
it OK. Maybe try it with a FTP program instead of your
browser?

>Sounds like the PDP-8 skip style ... Mode 1 Conditions are
>ANDED together Mode 2 Conditions are ORED together.

The PDP-8 "Group 2 (skip) microinstructions" allowed you
to AND/OR combine the primitive skip conditions (link,zero,sign)
to build compound conditionals for the skip sense; however, it
always skipped only one instruction.

ESKIP allows conditional execution of up to four
instructions, with the AND/XOR mode bit controlling how
the next four instructions are executed rather than
controlling the sense of skip condition as did the PDP-8.

In AND mode, ESKIP allows you to skip 1 to 4 instructions.

In XOR mode, it essentially creates a simple "if-then-else",
allowing conditional execution of only one of two groupings of
the following four instructions. Brian



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