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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Help please - kalemanav - Aug 2 15:11:00 2002
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Hi, Quick question. Can anyone please let me know if I can generate a clock with more frequency than input clock from a synthesisable verilog module.I appreciate your help. please take me as a novice to verilog HDL coding. I was actually trying to multiply a clock signal with a binary input of 8 bits. so if for example I have a input clock frequency of 100KHz my output clock depends on a 8bit bus value. If the bus value is 2, my output should be 200Khz(100 *2) and so on. Thanks a lot for the help. Best regards, kale |
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Re: Help please - Vikram Chandrasekhar - Aug 2 16:48:00 2002
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I assume that you are targetting it towards a FPGA. Xilinx, for example provides really neat clock buffers (CLKDLL in Virtex FPGA's/DCM in Virtex-2) that can multiply the input clock frequency by a pre-specified factor. Virtex-2 also has a BUFGMUX that helps you multiplex multiple clocks onto a common line based on a control signal. It has guaranteed skew, so there is little scope for asynchronism. Vikram Vikram Chandrasekhar Graduate Student Electrical and Computer Engg. Rice University Ph:(713)529 9819 (R) (713)348 2897 (O) www.ece.rice.edu/~cvikram/index.html On Fri, 2 Aug 2002, kalemanav wrote: > Hi, > Quick question. Can anyone please let me know if I can generate a > clock with more frequency than input clock from a synthesisable > verilog module.I appreciate your help. please take me as a novice to > verilog HDL coding. > I was actually trying to multiply a clock signal with a binary input > of 8 bits. so if for example I have a input clock frequency of 100KHz > my output clock depends on a 8bit bus value. If the bus value is 2, > my output should be 200Khz(100 *2) and so on. > Thanks a lot for the help. > Best regards, > kale > To post a message, send it to: > To unsubscribe, send a blank message to: |
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Re: Help please - manav kale - Aug 2 17:39:00 2002
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Hi Vikram, Thanks a lot for the help. I understood completely what you are talking about. Thanks a lot for your time and help. I will spend sometime in xilinx website now. I appreciate it. Best Regards, kale, Manav --- Vikram Chandrasekhar <> wrote: > I assume that you are targetting it towards a FPGA. > Xilinx, for example > provides really neat clock buffers (CLKDLL in Virtex > FPGA's/DCM in > Virtex-2) that can multiply the input clock > frequency by a pre-specified > factor. > Virtex-2 also has a BUFGMUX that helps you multiplex > multiple clocks onto > a common line based on a control signal. It has > guaranteed skew, so there > is little scope for asynchronism. > > Vikram > Vikram Chandrasekhar > Graduate Student > Electrical and Computer Engg. > Rice University > Ph:(713)529 9819 (R) > (713)348 2897 (O) > www.ece.rice.edu/~cvikram/index.html > > On Fri, 2 Aug 2002, kalemanav wrote: > > > Hi, > > Quick question. Can anyone please let me know if I > can generate a > > clock with more frequency than input clock from a > synthesisable > > verilog module.I appreciate your help. please take > me as a novice to > > verilog HDL coding. > > I was actually trying to multiply a clock signal > with a binary input > > of 8 bits. so if for example I have a input clock > frequency of 100KHz > > my output clock depends on a 8bit bus value. If > the bus value is 2, > > my output should be 200Khz(100 *2) and so on. > > Thanks a lot for the help. > > Best regards, > > kale > > > > > > To post a message, send it to: > > > To unsubscribe, send a blank message to: > > > > > > > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > ===== $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ The world belongs to those who dare to dream great and achieve it. Kale, manav. 1117 citypark ave #c-14,Fort collins,CO-80521 USA ph#970-484-3848; http://www.engr.colostate.edu/~manav $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ __________________________________________________ |
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RE: Help please - Ricky S. Nite - Aug 5 0:23:00 2002
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Hello, this is just a warning: make sure the CLKDLLs are properly located - sometimes the Xilinx ISE compiler cannot place them properly, especially for large designs. It's much better if you manually add the location constraints to the *.ucf file, for example: INST I1_I55 LOC=DLL0; INST I1_I62 LOC=GCLKBUF0; ... where I1_I55 and I1_I62 are the instance names in your schematic. I spent around 3 days debugging this one.. :) Ricky S. Nite Design Engineer ViCon -----Original Message----- From: manav kale [mailto:] Sent: Saturday, August 03, 2002 6:39 AM To: Subject: Re: [fpga-cpu] Help please Hi Vikram, Thanks a lot for the help. I understood completely what you are talking about. Thanks a lot for your time and help. I will spend sometime in xilinx website now. I appreciate it. Best Regards, kale, Manav --- Vikram Chandrasekhar <> wrote: > I assume that you are targetting it towards a FPGA. > Xilinx, for example > provides really neat clock buffers (CLKDLL in Virtex > FPGA's/DCM in > Virtex-2) that can multiply the input clock > frequency by a pre-specified > factor. > Virtex-2 also has a BUFGMUX that helps you multiplex > multiple clocks onto > a common line based on a control signal. It has > guaranteed skew, so there > is little scope for asynchronism. > > Vikram > Vikram Chandrasekhar > Graduate Student > Electrical and Computer Engg. > Rice University > Ph:(713)529 9819 (R) > (713)348 2897 (O) > www.ece.rice.edu/~cvikram/index.html > > On Fri, 2 Aug 2002, kalemanav wrote: > > > Hi, > > Quick question. Can anyone please let me know if I > can generate a > > clock with more frequency than input clock from a > synthesisable > > verilog module.I appreciate your help. please take > me as a novice to > > verilog HDL coding. > > I was actually trying to multiply a clock signal > with a binary input > > of 8 bits. so if for example I have a input clock > frequency of 100KHz > > my output clock depends on a 8bit bus value. If > the bus value is 2, > > my output should be 200Khz(100 *2) and so on. > > Thanks a lot for the help. > > Best regards, > > kale > > > > > > To post a message, send it to: > > > To unsubscribe, send a blank message to: > > > > > > > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > ===== $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ The world belongs to those who dare to dream great and achieve it. Kale, manav. 1117 citypark ave #c-14,Fort collins,CO-80521 USA ph#970-484-3848; http://www.engr.colostate.edu/~manav $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ __________________________________________________ To post a message, send it to: To unsubscribe, send a blank message to: |
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RE: Help please - Vikram Chandrasekhar - Aug 5 1:49:00 2002
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Hi there, I did'nt quite get that. What do I1_155,I1_162 stand for? Are they specific to your schematic or do they stand for some keywords. And what are the "fatal consequences" of not doing so? :) Can you please clarify. Thanks Vikram On Mon, 5 Aug 2002, Ricky S. Nite wrote: > Hello, > > this is just a warning: make sure the CLKDLLs are properly > located - sometimes the Xilinx ISE compiler cannot place > them properly, especially for large designs. It's much > better if you manually add the location constraints to > the *.ucf file, for example: > > INST I1_I55 LOC=DLL0; > INST I1_I62 LOC=GCLKBUF0; > ... > > where I1_I55 and I1_I62 are the instance names in your schematic. > I spent around 3 days debugging this one.. :) > > Ricky S. Nite > Design Engineer > ViCon > > -----Original Message----- > From: manav kale [mailto:] > Sent: Saturday, August 03, 2002 6:39 AM > To: > Subject: Re: [fpga-cpu] Help please > Hi Vikram, Thanks a lot for the help. I understood > completely what you are talking about. Thanks a lot > for your time and help. I will spend sometime in > xilinx website now. > I appreciate it. > Best Regards, > kale, Manav > > --- Vikram Chandrasekhar <> wrote: > > I assume that you are targetting it towards a FPGA. > > Xilinx, for example > > provides really neat clock buffers (CLKDLL in Virtex > > FPGA's/DCM in > > Virtex-2) that can multiply the input clock > > frequency by a pre-specified > > factor. > > Virtex-2 also has a BUFGMUX that helps you multiplex > > multiple clocks onto > > a common line based on a control signal. It has > > guaranteed skew, so there > > is little scope for asynchronism. > > > > Vikram > > > > > > Vikram Chandrasekhar > > Graduate Student > > Electrical and Computer Engg. > > Rice University > > Ph:(713)529 9819 (R) > > (713)348 2897 (O) > > www.ece.rice.edu/~cvikram/index.html > > > > On Fri, 2 Aug 2002, kalemanav wrote: > > > > > Hi, > > > Quick question. Can anyone please let me know if I > > can generate a > > > clock with more frequency than input clock from a > > synthesisable > > > verilog module.I appreciate your help. please take > > me as a novice to > > > verilog HDL coding. > > > I was actually trying to multiply a clock signal > > with a binary input > > > of 8 bits. so if for example I have a input clock > > frequency of 100KHz > > > my output clock depends on a 8bit bus value. If > > the bus value is 2, > > > my output should be 200Khz(100 *2) and so on. > > > Thanks a lot for the help. > > > Best regards, > > > kale > > > > > > > > > To post a message, send it to: > > > > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > > > > > > > > > > To post a message, send it to: > > > > To unsubscribe, send a blank message to: > > > > > > > > > > ===== > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > The world belongs to those who dare to dream great and achieve it. > Kale, manav. > 1117 citypark ave #c-14,Fort collins,CO-80521 USA ph#970-484-3848; > http://www.engr.colostate.edu/~manav > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > > __________________________________________________ > > To post a message, send it to: > To unsubscribe, send a blank message to: > > To post a message, send it to: > To unsubscribe, send a blank message to: |
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RE: Help please - Ricky S. Nite - Aug 5 2:00:00 2002
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Hello Vikram, Im sorry.. Ix_xx are just specific instance names automatically assigned to a component symbol (e.g. DLL, CLKBUF) when you make your design using the schematic entry tool of Xilinx ISE. so the syntax is: INST <instance_name> LOC=<resource_name> There's really nothing fatal - the compiler just issues some warnings/errors , esp if it's a large program. Basically the idea is to manually fix the placement of the DLL components before compilation so the compiler won't have to worry about it anymore :) Ricky Nite -----Original Message----- From: Vikram Chandrasekhar [mailto:] Sent: Monday, August 05, 2002 2:50 PM To: Subject: RE: [fpga-cpu] Help please Hi there, I did'nt quite get that. What do I1_155,I1_162 stand for? Are they specific to your schematic or do they stand for some keywords. And what are the "fatal consequences" of not doing so? :) Can you please clarify. Thanks Vikram On Mon, 5 Aug 2002, Ricky S. Nite wrote: > Hello, > > this is just a warning: make sure the CLKDLLs are properly > located - sometimes the Xilinx ISE compiler cannot place > them properly, especially for large designs. It's much > better if you manually add the location constraints to > the *.ucf file, for example: > > INST I1_I55 LOC=DLL0; > INST I1_I62 LOC=GCLKBUF0; > ... > > where I1_I55 and I1_I62 are the instance names in your schematic. > I spent around 3 days debugging this one.. :) > > Ricky S. Nite > Design Engineer > ViCon > > -----Original Message----- > From: manav kale [mailto:] > Sent: Saturday, August 03, 2002 6:39 AM > To: > Subject: Re: [fpga-cpu] Help please > Hi Vikram, Thanks a lot for the help. I understood > completely what you are talking about. Thanks a lot > for your time and help. I will spend sometime in > xilinx website now. > I appreciate it. > Best Regards, > kale, Manav > > --- Vikram Chandrasekhar <> wrote: > > I assume that you are targetting it towards a FPGA. > > Xilinx, for example > > provides really neat clock buffers (CLKDLL in Virtex > > FPGA's/DCM in > > Virtex-2) that can multiply the input clock > > frequency by a pre-specified > > factor. > > Virtex-2 also has a BUFGMUX that helps you multiplex > > multiple clocks onto > > a common line based on a control signal. It has > > guaranteed skew, so there > > is little scope for asynchronism. > > > > Vikram > > > > > > Vikram Chandrasekhar > > Graduate Student > > Electrical and Computer Engg. > > Rice University > > Ph:(713)529 9819 (R) > > (713)348 2897 (O) > > www.ece.rice.edu/~cvikram/index.html > > > > On Fri, 2 Aug 2002, kalemanav wrote: > > > > > Hi, > > > Quick question. Can anyone please let me know if I > > can generate a > > > clock with more frequency than input clock from a > > synthesisable > > > verilog module.I appreciate your help. please take > > me as a novice to > > > verilog HDL coding. > > > I was actually trying to multiply a clock signal > > with a binary input > > > of 8 bits. so if for example I have a input clock > > frequency of 100KHz > > > my output clock depends on a 8bit bus value. If > > the bus value is 2, > > > my output should be 200Khz(100 *2) and so on. > > > Thanks a lot for the help. > > > Best regards, > > > kale > > > > > > > > > To post a message, send it to: > > > > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > > > > > > > > > > To post a message, send it to: > > > > To unsubscribe, send a blank message to: > > > > > > > > > > ===== > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > The world belongs to those who dare to dream great and achieve it. > Kale, manav. > 1117 citypark ave #c-14,Fort collins,CO-80521 USA ph#970-484-3848; > http://www.engr.colostate.edu/~manav > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > > __________________________________________________ > > To post a message, send it to: > To unsubscribe, send a blank message to: > > To post a message, send it to: > To unsubscribe, send a blank message to: To post a message, send it to: To unsubscribe, send a blank message to: |
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RE: Help please - Vikram Chandrasekhar - Aug 5 2:07:00 2002
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Hi Ricky Thanks for the tip. It may be useful someday! :) Vikram Vikram Chandrasekhar Graduate Student Electrical and Computer Engg. Rice University Ph:(713)529 9819 (R) (713)348 2897 (O) www.ece.rice.edu/~cvikram/index.html On Mon, 5 Aug 2002, Ricky S. Nite wrote: > Hello Vikram, > > Im sorry.. Ix_xx are just specific instance names automatically > assigned to a component symbol (e.g. DLL, CLKBUF) when you make > your design using the schematic entry tool of Xilinx ISE. so the > syntax is: > > INST <instance_name> LOC=<resource_name> > > There's really nothing fatal - the compiler just issues some > warnings/errors , esp if it's a large program. Basically the > idea is to manually fix the placement of the DLL components > before compilation so the compiler won't have to worry about it > anymore :) > > Ricky Nite > -----Original Message----- > From: Vikram Chandrasekhar [mailto:] > Sent: Monday, August 05, 2002 2:50 PM > To: > Subject: RE: [fpga-cpu] Help please > Hi there, > > I did'nt quite get that. What do I1_155,I1_162 stand for? > Are they specific to your schematic or do they stand for some keywords. > > And what are the "fatal consequences" of not doing so? :) > > Can you please clarify. > Thanks > Vikram > On Mon, 5 Aug 2002, Ricky S. Nite wrote: > > > Hello, > > > > this is just a warning: make sure the CLKDLLs are properly > > located - sometimes the Xilinx ISE compiler cannot place > > them properly, especially for large designs. It's much > > better if you manually add the location constraints to > > the *.ucf file, for example: > > > > INST I1_I55 LOC=DLL0; > > INST I1_I62 LOC=GCLKBUF0; > > ... > > > > where I1_I55 and I1_I62 are the instance names in your schematic. > > I spent around 3 days debugging this one.. :) > > > > Ricky S. Nite > > Design Engineer > > ViCon > > > > > > > > -----Original Message----- > > From: manav kale [mailto:] > > Sent: Saturday, August 03, 2002 6:39 AM > > To: > > Subject: Re: [fpga-cpu] Help please > > > > > > Hi Vikram, Thanks a lot for the help. I understood > > completely what you are talking about. Thanks a lot > > for your time and help. I will spend sometime in > > xilinx website now. > > I appreciate it. > > Best Regards, > > kale, Manav > > > > --- Vikram Chandrasekhar <> wrote: > > > I assume that you are targetting it towards a FPGA. > > > Xilinx, for example > > > provides really neat clock buffers (CLKDLL in Virtex > > > FPGA's/DCM in > > > Virtex-2) that can multiply the input clock > > > frequency by a pre-specified > > > factor. > > > Virtex-2 also has a BUFGMUX that helps you multiplex > > > multiple clocks onto > > > a common line based on a control signal. It has > > > guaranteed skew, so there > > > is little scope for asynchronism. > > > > > > Vikram > > > > > > > > > Vikram Chandrasekhar > > > Graduate Student > > > Electrical and Computer Engg. > > > Rice University > > > Ph:(713)529 9819 (R) > > > (713)348 2897 (O) > > > www.ece.rice.edu/~cvikram/index.html > > > > > > On Fri, 2 Aug 2002, kalemanav wrote: > > > > > > > Hi, > > > > Quick question. Can anyone please let me know if I > > > can generate a > > > > clock with more frequency than input clock from a > > > synthesisable > > > > verilog module.I appreciate your help. please take > > > me as a novice to > > > > verilog HDL coding. > > > > I was actually trying to multiply a clock signal > > > with a binary input > > > > of 8 bits. so if for example I have a input clock > > > frequency of 100KHz > > > > my output clock depends on a 8bit bus value. If > > > the bus value is 2, > > > > my output should be 200Khz(100 *2) and so on. > > > > Thanks a lot for the help. > > > > Best regards, > > > > kale > > > > > > > > > > > > To post a message, send it to: > > > > > > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > To post a message, send it to: > > > > > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > > > > > > > > ===== > > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > > The world belongs to those who dare to dream great and achieve it. > > Kale, manav. > > 1117 citypark ave #c-14,Fort collins,CO-80521 USA ph#970-484-3848; > > http://www.engr.colostate.edu/~manav > > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > > > > __________________________________________________ > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > > > > > > > > > To post a message, send it to: > To unsubscribe, send a blank message to: > > To post a message, send it to: > To unsubscribe, send a blank message to: |
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RE: Help please - manav kale - Aug 5 8:49:00 2002
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Dear Ricky, Thanks for the suggestion. best regards, kale --- "Ricky S. Nite" <> wrote: > Hello, > > this is just a warning: make sure the CLKDLLs are > properly > located - sometimes the Xilinx ISE compiler cannot > place > them properly, especially for large designs. It's > much > better if you manually add the location constraints > to > the *.ucf file, for example: > > INST I1_I55 LOC=DLL0; > INST I1_I62 LOC=GCLKBUF0; > ... > > where I1_I55 and I1_I62 are the instance names in > your schematic. > I spent around 3 days debugging this one.. :) > > Ricky S. Nite > Design Engineer > ViCon > > -----Original Message----- > From: manav kale [mailto:] > Sent: Saturday, August 03, 2002 6:39 AM > To: > Subject: Re: [fpga-cpu] Help please > Hi Vikram, Thanks a lot for the help. I understood > completely what you are talking about. Thanks a lot > for your time and help. I will spend sometime in > xilinx website now. > I appreciate it. > Best Regards, > kale, Manav > > --- Vikram Chandrasekhar <> > wrote: > > I assume that you are targetting it towards a > FPGA. > > Xilinx, for example > > provides really neat clock buffers (CLKDLL in > Virtex > > FPGA's/DCM in > > Virtex-2) that can multiply the input clock > > frequency by a pre-specified > > factor. > > Virtex-2 also has a BUFGMUX that helps you > multiplex > > multiple clocks onto > > a common line based on a control signal. It has > > guaranteed skew, so there > > is little scope for asynchronism. > > > > Vikram > > > > > > Vikram Chandrasekhar > > Graduate Student > > Electrical and Computer Engg. > > Rice University > > Ph:(713)529 9819 (R) > > (713)348 2897 (O) > > www.ece.rice.edu/~cvikram/index.html > > > > On Fri, 2 Aug 2002, kalemanav wrote: > > > > > Hi, > > > Quick question. Can anyone please let me know if > I > > can generate a > > > clock with more frequency than input clock from > a > > synthesisable > > > verilog module.I appreciate your help. please > take > > me as a novice to > > > verilog HDL coding. > > > I was actually trying to multiply a clock signal > > with a binary input > > > of 8 bits. so if for example I have a input > clock > > frequency of 100KHz > > > my output clock depends on a 8bit bus value. If > > the bus value is 2, > > > my output should be 200Khz(100 *2) and so on. > > > Thanks a lot for the help. > > > Best regards, > > > kale > > > > > > > > > To post a message, send it to: > > > > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > > > > > > > > > > To post a message, send it to: > > > > To unsubscribe, send a blank message to: > > > > > > > > > > ===== > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > The world belongs to those who dare to dream great > and achieve it. > Kale, manav. > 1117 citypark ave #c-14,Fort collins,CO-80521 USA > ph#970-484-3848; > http://www.engr.colostate.edu/~manav > $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ > > __________________________________________________ > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > ===== $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ The world belongs to those who dare to dream great and achieve it. Kale, manav. 1117 citypark ave #c-14,Fort collins,CO-80521 USA ph#970-484-3848; http://www.engr.colostate.edu/~manav $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ __________________________________________________ |
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